NAND Flash Soft Decoding Using Extrinsic Page Information

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Solution Overview

Problem

Flash memory devices, such as NAND flash memory, experience errors due to noise and interference during programming and read operations, leading to inaccuracies in stored information bits, which existing error correction codes struggle to address effectively, especially under high stress conditions.

Innovation Solution

A soft decoder system that performs error correction by utilizing extrinsic page information from adjacent pages in a memory block, allowing for secondary decoding processes and log-likelihood ratio (LLR) allocation to improve decoding accuracy without additional latency, by modifying voltage thresholds and allocating LLRs based on page information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional hard decoding is used, then decoding speed is fast, but error correction capability is insufficient under high noise conditions

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the parameter of decoding input from hard decisions (0/1) to soft decisions (log-likelihood ratios with continuous values). This allows the decoder to utilize magnitude information from read operations to improve error correction capability while maintaining computational efficiency through modified BCH decoding algorithms that process soft information without requiring complex iterative processes.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If additional read operations are performed to gather extrinsic page information, then decoding capability is improved, but latency increases

Engineering Contradiction:
Improvedecoding capabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by reading all pages in a row during the initial read operation and storing extrinsic page information in buffers before the decoding process. This allows the decoder to access extrinsic information without requiring additional read operations, thereby improving decoding capability while maintaining low latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces buffer memory as an intermediary to store extrinsic page information read from adjacent pages. This intermediary allows the decoder to access additional information without performing additional NAND reads, effectively decoupling the read operation from the decoding operation and reducing latency while improving capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If voltage thresholds are modified for soft sampling, then decoding reliability is improved, but read operation complexity increases

Engineering Contradiction:
Improvedecoding reliabilityVSAvoidread operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the voltage threshold modification process into discrete steps: first reading with initial thresholds, then modifying thresholds based on extrinsic information, and finally performing soft sampling with adjusted thresholds. This segmentation allows systematic improvement of decoding reliability while managing complexity through structured processing.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12119075B2Efficient soft decoding of error correction code via extrinsic bit information
Publication Date: 2024.10.15 KIOXIA CORP
  • US12119075B2 patent drawing
  • US12119075B2 patent drawing
  • US12119075B2 patent drawing

AI summary

Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.