Multi-Value NAND Flash Error Correction via Soft-Value Read Voltages
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Solution Overview
Problem
Multi-value NAND cell type flash memory systems face increased failure bit probabilities and reduced data reliability due to smaller threshold voltage margins as memory cells are miniaturized, which conventional error correction circuits struggle to address effectively.
Innovation Solution
A non-volatile semiconductor storage system that includes a memory cell array with bit-line and word-line control circuits capable of applying specific read voltages to generate soft-values and calculate the likelihood of stored data, complementing the first error correction circuit with a second error correction circuit to handle uncorrectable errors without increasing redundant data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-value storage is implemented to increase memory capacity, then storage density is improved, but threshold voltage margins become smaller and error probability increases
Solution Approach 1:
The patent changes the read voltage parameter from a single fixed voltage to multiple variable voltages. By applying different read voltages (first read voltage and second read voltage) that are offset from each other, the system can detect threshold voltage shifts more accurately and correct errors without requiring larger margins between threshold voltage distributions.
Solution Approach 2:
The patent implements a feedback mechanism where the detection result from the first read voltage is used to determine whether to apply a second read voltage. The error detection circuit feeds back information about detected errors to the control circuit, which then decides whether to perform correction using the second read voltage, creating a closed-loop error correction system.
2Reliability
If conventional ECC circuits are used to correct errors, then data reliability is improved, but they cannot effectively handle write errors in multi-value storage
Solution Approach 1:
The patent makes the error correction system dynamic by adjusting the read voltage based on detected errors. Instead of using a fixed correction approach, the system dynamically switches between different read voltages and correction methods depending on the error conditions detected, allowing it to adapt to various error scenarios in multi-value storage.
Solution Approach 2:
The patent segments the error correction process into multiple stages: first detection using a first read voltage, then conditional second detection using a second read voltage with opposite offset direction. This segmented approach allows the system to handle different types of errors that would be indistinguishable with a single read voltage.
3Area of moving object
If memory cells are miniaturized to increase integration density, then device integration is improved, but failure bit probability increases greatly
Solution Approach 1:
The patent compensates for miniaturization effects by changing the read voltage parameters. By applying voltages with opposite offsets and comparing results, the system can detect and correct threshold voltage variations that become more significant as memory cells are miniaturized, thereby maintaining yield despite smaller cell sizes.
Data Source
AI summary
In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.