NAND Flash Soft-Bit Read Voltage Tracking for Better Decoding
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Solution Overview
Problem
Current memory systems face challenges in optimizing soft bit read voltages for NAND flash memories, leading to reduced mutual information content and decoding success probability due to fixed offset-based approaches that do not consider the dynamic nature of threshold voltage distributions.
Innovation Solution
The memory system dynamically optimizes soft bit read voltages based on tracking results, using calculated inclination values and stress information to set appropriate shift values, thereby improving the accuracy of soft bit decoding and increasing mutual information content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed offset-based approaches are used to set soft bit read voltages, then the device complexity is reduced, but the mutual information content and decoding success probability deteriorate
Solution Approach 1:
The patent implements dynamic adjustment of soft bit read voltages based on tracking results. The memory controller performs tracking reads at different voltages, calculates inclination values from the results, and dynamically sets optimal soft bit read voltages according to the actual threshold voltage distribution shape. This transforms the fixed voltage setting into a dynamic, adaptive process that responds to changing memory conditions, thereby maintaining high mutual information content without excessive complexity.
Solution Approach 2:
The patent introduces a feedback mechanism where tracking reads are performed to obtain actual threshold voltage distribution information, which is then used to adjust the soft bit read voltages. The inclination calculation based on tracking results provides feedback about the distribution shape, enabling the system to optimize voltages according to real conditions. This feedback loop ensures high decoding success probability while managing complexity through intelligent control.
2Ease of operation
If fixed offset-based approaches are used to set soft bit read voltages, then the ease of operation is improved, but the decoding success probability deteriorates
Solution Approach 1:
The memory controller performs self-optimization by automatically conducting tracking reads, calculating inclination values, and determining optimal soft bit read voltages based on the actual threshold voltage distribution. This self-service mechanism eliminates the need for manual voltage calibration while ensuring high decoding success probability. The system adapts to changing conditions autonomously, maintaining reliability without sacrificing operational simplicity.
3Loss of information
If dynamic optimization of soft bit read voltages is performed, then the mutual information content is improved, but the device complexity increases
Solution Approach 1:
The patent changes the parameter of read voltage from a fixed value to a dynamically adjusted parameter based on tracking results. By calculating inclination values from tracking reads and using these to determine optimal soft bit read voltages, the system adapts voltage parameters to match the actual threshold voltage distribution shape. This parameter change approach maximizes mutual information content while managing complexity through mathematical optimization rather than hardware complexity.
4Reliability
If dynamic optimization of soft bit read voltages is performed, then the decoding success probability is improved, but the ease of operation deteriorates
Solution Approach 1:
The patent performs tracking reads and calculates inclination values in advance to determine optimal soft bit read voltages before actual data reading. This preliminary action prepares the system with optimized voltage settings based on the current threshold voltage distribution, ensuring high decoding success probability. The complexity of dynamic optimization is confined to the preliminary calibration phase, while the actual data reading operation remains simple and easy to execute.
Data Source
AI summary
A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.