NAND Flash Memory Sidewall Spacer Patterning
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Solution Overview
Problem
Conventional photolithography is limited in creating very small features for memory chip manufacturing, requiring numerous layers and process steps, which complicates control of critical dimensions and increases costs.
Innovation Solution
The method employs sidewall spacers to form features one-third the size of those achievable with direct patterning, using a series of process steps involving mandrels, hard mask materials, and etching to create smaller dimensions with good control, including the use of Spin-On Carbon and Silicon Dioxide spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to create small features, then manufacturing process is simple, but manufacturing precision deteriorates due to inability to achieve very small dimensions
Solution Approach 1:
The patent applies segmentation by dividing the single patterning step into multiple sequential patterning operations. First, mandrels are formed with initial pitch, then sidewall spacers are deposited and patterned to create intermediate features, followed by removal of mandrels and formation of additional hard mask portions. This multi-stage segmentation enables achieving 1/3 of the original photolithography feature size while maintaining control over each individual step.
Solution Approach 2:
The patent employs preliminary action by pre-forming mandrels and sidewall spacers before final pattern transfer. The mandrels are created first as sacrificial structures, then sidewall spacers are deposited on them to define the final feature locations. This preliminary structuring allows the final etching step to precisely reproduce the desired pattern with reduced pitch without requiring direct single-step photolithography.
2Manufacturing precision
If more layers and process steps are used to achieve smaller features, then manufacturing precision improves, but device complexity increases and costs rise
Solution Approach 1:
The patent merges multiple patterning functions into an integrated process flow. The formation of sidewall spacers, mandrel removal, and hard mask deposition are combined in a sequence that achieves triple patterning (1/3 pitch reduction) while using fewer total steps than conventional approaches. The hard mask material serves dual purposes as both the etch mask and the final pattern definition layer, merging protective and patterning functions.
Solution Approach 2:
The patent uses sidewall spacers as intermediary structures that mediate between the photolithographically-defined mandrels and the final hard mask pattern. These spacers act as self-aligned intermediaries that automatically position the final features at precise intervals (1/3 of original pitch) without requiring additional alignment steps, thus improving critical dimension control while limiting complexity growth.
3Manufacturing precision
If direct patterning is used, then process is simpler, but pitch reduction is limited and cannot achieve one-third dimensions
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional structuring by forming vertical sidewall spacers on mandrels. This dimensional transition allows the horizontal pitch to be reduced by a factor of three while using the vertical dimension for spacer thickness control. The sidewall spacers extend vertically from the mandrel surfaces, creating a 3D structure that enables superior pitch multiplication compared to conventional 2D lithographic approaches.
Solution Approach 2:
The patent changes key process parameters including spacer material composition (e.g., silicon nitride, silicon oxide), deposition thickness (controlled to achieve desired horizontal spacing), and etch selectivity ratios. By adjusting these parameters, the process achieves consistent 1/3 pitch reduction across different feature sizes and densities, maintaining ease of manufacture through parameter optimization rather than process complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced pitch by a factor of three with fewer layers and steps, maintaining precise control of critical dimensions, thus enabling the formation of smaller memory cell features efficiently.
Implementation Method 1
subsequently depositing a hard mask material on the sidewall spacers to fill the gaps between sidewall spacers and partially fill spaces where mandrels were removed
Implementation Method 2
subsequently etching back the hard mask material to leave separate hard mask portions, two portions where each mandrel was removed, and one portion between sidewall spacers of neighboring mandrels
Data Source
AI summary
A NAND flash memory array is initially patterned by forming a plurality of sidewall spacers according along sides of patterned portions of material. The pattern of sidewall spacers is then used to form a second pattern of hard mask portions including first hard mask portions defined on both sides by sidewall spacers and second hard mask portions defined on only one side by sidewall spacers.