NAND Flash Memory Status Output via Signal Edge Detection
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Solution Overview
Problem
Conventional NAND flash memory systems require a two-clock-cycle waiting time to obtain the current status, which consumes time and reduces system performance, especially when frequently needed after programming or erasing operations.
Innovation Solution
A status output method in NAND flash memory that sets the ALE and CLE signals to 1 and the WE# signal to 1, allowing the LUN status signal to be output upon detection of a falling edge of the RE# signal, with the option to store this status in a register for faster retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the conventional two-clock-cycle status output method is used, then the status can be obtained through standard commands, but the system performance is reduced due to the waiting time
Solution Approach 1:
The patent pre-loads the status signal into a buffer register during the programming operation, so that when the programming completes, the status is already ready for immediate output. This eliminates the need to wait for status after programming, directly reducing status acquisition time and improving system performance
Solution Approach 2:
The patent makes the status output process continuous by buffering the status signal during programming operations. Instead of idle waiting, the system continuously prepares status information in advance, ensuring that status data is always ready when needed, thereby eliminating downtime and improving overall productivity
2Speed
If data is written in advance to prepare for status output, then the status can be retrieved faster, but additional write operations are required which complicate the process
Solution Approach 1:
The patent combines the status buffering function with the existing buffer register structure already present in NAND flash memory controllers. By reusing the existing buffer infrastructure for dual purposes (data buffering and status buffering), the patent achieves faster status output without adding significant complexity to the control process
Solution Approach 2:
The buffer register is designed to serve multiple functions: it can buffer both data operations and status signals. This multi-functionality allows the same hardware structure to handle different operations, achieving fast status output while maintaining simple control logic that can handle both data and status operations through a unified interface
Data Source
AI summary
The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.