NAND Flash Memory Sub-Bit Line Grouping for Leakage Reduction
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Solution Overview
Problem
Conventional NAND type flash memory devices experience significant leakage current issues during read operations due to the large number of drain select contact plugs, which can incorrectly determine programmed cells as erased cells.
Innovation Solution
The memory device is reconfigured by dividing cell blocks into groups with sub-bit lines allocated to each group, and group selectors connect only the sub-bit lines of the selected group to the main bit line, reducing the total leakage current by isolating unselected sub-bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of drain select contact plugs are used to connect multiple cell blocks to a single bit line, then the memory device achieves high integration and capacity, but the leakage current increases significantly causing read errors
Solution Approach 1:
The patent divides the bit line structure into sub-bit lines, with each sub-bit line serving a specific cell block. This segmentation isolates the leakage current to individual sub-bit lines, preventing it from affecting the entire bit line. The group selector transistor then selectively connects only the required sub-bit line to the main bit line during read operations, effectively managing the leakage current issue while maintaining high integration.
2Productivity
If multiple cell blocks are connected to one bit line to increase storage capacity, then device integration is improved, but read operation accuracy deteriorates due to leakage current affecting the bit line state
Solution Approach 1:
The group selector transistor acts as an intermediary between the sub-bit lines and the main bit line. During read operations, it selectively connects only the sub-bit line corresponding to the selected cell block to the main bit line, while isolating other sub-bit lines. This intermediary mechanism prevents leakage current from unselected cell blocks from corrupting the bit line state, thereby maintaining read operation accuracy despite high storage capacity.
3Speed
If all sub-bit lines are continuously connected to the main bit line to ensure data access, then read speed is maintained, but leakage current continuously discharges the bit line causing operational errors
Solution Approach 1:
The connection between sub-bit lines and the main bit line is made dynamic through the group selector transistor, which is controlled by a group select signal. During read operations, the transistor dynamically connects the required sub-bit line to the main bit line, enabling fast data access. When not in use, the transistor dynamically disconnects the sub-bit lines, preventing continuous leakage current discharge. This dynamic control mechanism maintains both read speed and operational reliability.
Data Source
AI summary
A nonvolatile memory device can improve its operation characteristic by reducing leakage current of a bit line in a read operation. The nonvolatile memory device includes a plurality of word lines, a plurality of main bit lines intersecting with the plurality of word lines, a plurality of cell blocks each including a plurality of cell strings, each of the cell strings including first and second select transistors and a plurality of memory cells, a plurality of sub bit lines commonly connected to the respective cell strings in same group, the cell blocks being grouped into a plurality of groups whose number is identical to or smaller than the number of the cell blocks, a plurality of group selectors configured to selectively connect the main bit lines to the sub bit lines of a selected group, and a plurality of page buffers configured to sense data of the memory cells through the main bit lines.