NAND Flash Sub-Page Coding for Multi-Level Error Correction
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Solution Overview
Problem
Multi-level NAND cell-type flash memory devices face challenges in accurately storing and reading multiple bits per memory cell due to narrowing threshold voltage intervals, leading to increased error probabilities and complexities in error correction schemes.
Innovation Solution
A non-volatile semiconductor memory device is designed with a memory cell array capable of storing N bits using variations in threshold voltage, incorporating a parity data adder circuit, frame converter circuit, and programming circuit to divide data into subframes and store them in sub-pages, employing error correction schemes like LDPC codes for improved error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level storage is executed in one memory cell to increase memory capacity, then storage density is improved, but the interval between adjacent threshold voltages becomes narrower resulting in increased error probability
Solution Approach 1:
The invention divides the multi-level data into upper bit group and lower bit group, and further segments each group into multiple sub-groups. Each sub-group is stored in a separate sub-page with independent error correction codes. This segmentation allows error correction to be applied independently to each sub-group, improving reliability without sacrificing storage density.
Solution Approach 2:
The invention applies different error correction schemes to different sub-groups based on their specific error characteristics. The upper bit group and lower bit group can use different error correction codes tailored to their respective error probabilities, optimizing the local quality of error correction for each segment.
2Reliability
If error correction is applied to multi-level data, then reliability is improved, but device complexity increases due to different error correction schemes for upper and lower bit groups
Solution Approach 1:
By segmenting the data into sub-groups stored in separate sub-pages, the invention simplifies the error correction process. Each sub-page can be processed independently with its own error correction code, avoiding the complexity of applying complex error correction to the entire multi-level data block at once.
Solution Approach 2:
The invention changes the parameter of error correction granularity by applying error correction to smaller sub-groups rather than the entire data block. This parameter change reduces the computational complexity and configuration overhead while maintaining or improving error correction effectiveness.
3Quantity of substance
If threshold voltage intervals are narrowed to store more bits per cell, then storage capacity increases, but measurement precision deteriorates making it difficult to accurately read stored information
Solution Approach 1:
The invention segments the threshold voltage range into multiple sub-ranges, each corresponding to a sub-page. By detecting the threshold voltage in smaller, more discrete sub-ranges rather than attempting to detect a single wide range, the measurement precision is improved for each segment, enabling accurate reading even when the overall interval is narrow.
Data Source
AI summary
A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.