NAND Flash Transistor Doping for Breakdown Voltage
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Solution Overview
Problem
NAND flash devices face challenges in improving breakdown voltage characteristics and current characteristics, particularly in high-voltage transistors used in flash memory devices, which affect data storage and retrieval efficiency.
Innovation Solution
The design incorporates a NAND flash device with a peripheral circuit that includes transistors, a substrate, and a device isolation region, featuring a specific arrangement of lightly-doped and heavily-doped source and drain regions around gate structures to enhance breakdown voltage and current characteristics, including tapered trenches and strategically positioned doping regions to manage electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-voltage transistors are used in NAND flash devices, then data storage capacity is improved, but breakdown voltage characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating different doping regions with specific characteristics at different locations. The lightly-doped source and drain regions are positioned adjacent to the gate structure to manage electric fields locally, while heavily-doped regions are placed in specific areas to enhance current characteristics. This localized doping strategy allows the transistor to maintain high voltage tolerance while supporting increased storage capacity.
Solution Approach 2:
The patent changes physical parameters by implementing a multi-level doping structure where the lightly-doped source and drain regions have lower doping concentrations compared to conventional designs. This parameter change in doping concentration allows the transistor to sustain higher breakdown voltages while maintaining the current characteristics needed for high-capacity data storage operations.
2Quantity of substance
If high-voltage transistors are used in NAND flash devices, then data storage capacity is improved, but current characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating different doping regions with specific characteristics at different locations. The lightly-doped source and drain regions are positioned adjacent to the gate structure to manage electric fields locally, while heavily-doped regions are placed in specific areas to enhance current characteristics. This localized doping strategy allows the transistor to maintain high voltage tolerance while supporting increased storage capacity.
Solution Approach 2:
The patent segments the source and drain regions into multiple doping zones - lightly-doped regions adjacent to the gate and heavily-doped regions in other areas. This segmentation allows different parts of the transistor to perform specialized functions: the lightly-doped regions manage electric field distribution for high voltage tolerance, while the heavily-doped regions provide the current characteristics necessary for high-capacity data storage.
3Reliability
If source and drain regions are positioned adjacent to gate structure, then electric field management is improved, but device complexity increases
Solution Approach 1:
The patent segments the source and drain regions into multiple doping zones - lightly-doped regions adjacent to the gate and heavily-doped regions in other areas. This segmentation allows different parts of the transistor to perform specialized functions: the lightly-doped regions manage electric field distribution for high voltage tolerance, while the heavily-doped regions provide the current characteristics necessary for high-capacity data storage.
Solution Approach 2:
The patent changes physical parameters by implementing a multi-level doping structure where the lightly-doped source and drain regions have lower doping concentrations compared to conventional designs. This parameter change in doping concentration allows the transistor to sustain higher breakdown voltages while maintaining the current characteristics needed for high-capacity data storage operations.
Data Source
AI summary
A NAND flash device may include a peripheral circuit including a transistor, a substrate, and a device isolation region defining an active region of the substrate. The transistor may include a first gate structure on the active region. The transistor may include source and drain regions extending in a first direction in the active region on both sides of the first gate structure, which may include a first lightly-doped source and drain region adjacent to the first gate structure and a second lightly-doped source and drain region integrally connected thereto. The second lightly-doped source and drain region may be arranged farther from the first gate structure than the first lightly-doped source and drain region. The second lightly-doped source and drain region may have a smaller width in the second direction than a width of the first lightly-doped source and drain region in the second direction.