NAND Flash Two-Step Erase Inhibits Parasitic Charge
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Solution Overview
Problem
Existing nonvolatile memory devices, such as NAND-type flash memories, face issues with parasitic charge accumulation during erase operations, leading to potential over-erase conditions after repeated program/erase cycles due to strong fringing field strengths.
Innovation Solution
The method involves a two-step erase operation where the first and second pluralities of nonvolatile memory cells in a NAND-type string are selectively erased while biased at unequal voltages, with the second plurality in a blocking condition to inhibit erasure, and vice versa, using unequal erase and blocking voltages applied to functional and dummy word lines to manage electric field strengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional erase operation is performed on NAND-type flash memory, then erasure of memory cells is achieved, but parasitic charge accumulation occurs leading to over-erase conditions
Solution Approach 1:
The erase operation is divided into multiple sequential phases with different voltage conditions. First, a preliminary erase phase erases selected memory cells while blocking others. Then, a second erase phase completes the erasure of previously blocked cells. This segmentation prevents simultaneous strong fringing fields across all cells, thereby inhibiting parasitic charge accumulation while achieving complete erasure.
Solution Approach 2:
The erase operation uses periodic voltage application with distinct phases. During the first phase, word lines are alternately biased at erase voltage and blocking voltage. After a first time period, voltages are switched for the second phase. This periodic action controls fringing field strength over time, preventing excessive hole transfer to the charge trap layer while maintaining erasure effectiveness.
2Productivity
If strong fringing field strength is used during erase operations, then erasure efficiency is improved, but parasitic charge accumulation increases causing over-erase
Solution Approach 1:
Different voltage conditions are applied to different word lines and memory cell groups during the erase operation. Selected word lines receive erase voltage to enable efficient erasure, while other word lines receive blocking voltage to prevent parasitic charge accumulation. This local differentiation of voltage quality allows efficient erasure where needed while preventing harm where not needed.
Solution Approach 2:
The voltage parameters applied to word lines are dynamically changed during the erase operation. Erase voltage magnitude and polarity are adjusted based on which memory cells need erasure versus which cells should be protected from parasitic charging. This parameter modulation controls fringing field strength to optimize both erasure efficiency and prevent over-erase conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach inhibits excessive hole transfer and prevents over-erase conditions by maintaining controlled electric field strengths, ensuring reliable operation over the lifespan of the memory device.
Implementation Method 1
inhibiting fringing field strengths that may otherwise cause excessive hole transfer to the charge trap layer
Implementation Method 2
strong fringing field strengths during erase operations
Data Source
AI summary
Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the even-numbered nonvolatile memory cells. This operation to selectively erase the even-numbered nonvolatile memory cells may include erasing the even-numbered nonvolatile memory cells while simultaneously biasing the odd-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the odd-numbered nonvolatile memory cells. The operation to selectively erase the odd-numbered nonvolatile memory cells may include erasing the odd-numbered nonvolatile memory cells while simultaneously biasing the even-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the even-numbered nonvolatile memory cells.