Variable Wiring Resistance for NAND Flash Multi-Plane Charging
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Solution Overview
Problem
In NAND flash memory devices, the increase in memory capacity through multi-plane configuration leads to varying load capacitance and charge time, which deteriorates operation margin due to the difficulty in varying the power supply voltage generating circuit's capability in accordance with the number of selected planes.
Innovation Solution
A semiconductor integrated circuit device with a memory cell array configured in a multi-plane structure, incorporating a power supply voltage generating circuit that includes a voltage generating circuit, a plane select number detection circuit, and a resistance variable circuit to adjust wiring resistance based on the number of selected planes, allowing for uniform charging time regardless of the number of planes selected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-plane configuration is used to increase memory capacity, then memory capacity is improved, but operation margin deteriorates due to varying load capacitance and charge time
Solution Approach 1:
The patent applies dynamics by making the wiring resistance variable according to the number of selected planes. The resistance variable circuit adjusts the resistance value dynamically: when more planes are selected, the resistance is reduced to maintain consistent charge time despite increased load capacitance. This dynamic adjustment resolves the contradiction by adapting the circuit parameters to operating conditions, ensuring reliable operation across different plane selection scenarios while maintaining high memory capacity.
2Productivity
If the number of selected planes increases, then memory capacity utilization is improved, but charge time varies and operation margin deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the wiring resistance parameter based on the number of selected planes. The resistance variable circuit receives signals indicating the number of selected planes and adjusts the resistance accordingly. When more planes are selected (higher productivity), the resistance is reduced to compensate for increased load capacitance, thereby maintaining consistent charge time. This parameter adjustment resolves the contradiction between memory capacity utilization and charge time consistency.
3Device complexity
If a common power supply voltage generating circuit is used for multiple planes, then device complexity is reduced, but it becomes difficult to vary the generating circuit's capability in accordance with the number of selected planes
Solution Approach 1:
The patent introduces an intermediary element - the resistance variable circuit - between the common power supply voltage generating circuit and the memory cell arrays. This intermediary allows the simple common power supply circuit to adapt to different operating conditions by adjusting the effective resistance seen by each plane. The resistance variable circuit acts as a mediator that provides adaptability without requiring complex individual power supply circuits for each plane, thus resolving the contradiction between device complexity and adaptability.
Data Source
AI summary
A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.