NAND Flash Memory Verify-Failure Detection Logic Gate Chain
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Solution Overview
Problem
Existing NAND flash memory technologies face challenges in accurately counting verify-failed bits during data writing operations, leading to inefficiencies and reduced detection accuracy due to noise and transistor variation, which affects the pseudo-pass function and overall writing speed.
Innovation Solution
A semiconductor memory device configuration that includes a detector with a logic gate chain and a digital counter, where the presence or absence of verify-failed bits is indicated by a logic level, allowing the counter to count the number of times this level is present, thereby improving detection accuracy and speed while being resistant to noise and transistor variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If a circuit technology of counting the number of verify-failed bits is implemented, then the pseudo-pass function can be achieved, but the detection accuracy is reduced due to noise and transistor variation
Solution Approach 1:
The detection process is segmented into multiple independent detection units, each handling a specific column. Each detection unit contains its own detection circuit that independently counts verify-failed bits without interference from other columns, thereby isolating noise and transistor variation effects to individual segments rather than affecting the entire detection system.
Solution Approach 2:
A detection circuit acts as an intermediary between the memory cell array and the control logic. This detection circuit includes detection units with sense amplifiers and latch circuits that mediate the verification process, converting raw memory cell states into reliable verification results while filtering out noise and transistor variation effects through the intermediary detection mechanism.
2Measurement precision
If transistor size is increased to improve detection accuracy, then noise and transistor variation effects are reduced, but the device area increases
Solution Approach 1:
The detection system is divided into multiple detection units, each with its own sense amplifier and latch circuit. This segmentation allows each unit to use optimally sized transistors for accurate detection without requiring the entire system to use oversized transistors, thereby achieving high detection accuracy while maintaining compact device area through efficient resource distribution.
Solution Approach 2:
The patent uses multiple copies of identical detection circuits (detection units) distributed across different columns. Each detection unit is a replicated copy with standardized transistor sizes, allowing the system to achieve high detection accuracy through the collective operation of multiple identical units rather than relying on a single large transistor, thus maintaining small device area while improving accuracy.
3Reliability
If verification is performed for all bits during writing, then data integrity is ensured, but the writing speed is reduced
Solution Approach 1:
The patent implements partial verification by counting verify-failed bits and comparing the count against a threshold value. Instead of requiring all bits to pass verification, the system performs verification on all bits but allows the write operation to proceed if the number of failed bits is within an acceptable range, thereby achieving sufficient data integrity while improving writing speed through selective acceptance of verification results.
Solution Approach 2:
The detection circuit provides feedback about the number of verify-failed bits to the control logic. This feedback mechanism allows the system to make informed decisions about whether to complete or retry the write operation based on the verification results, enabling fast completion when verification succeeds within acceptable limits while maintaining reliability through automated feedback-driven control.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a plurality of memory cells, a logic gate chain, and a counter. The memory cells are capable of retaining data and are associated with the columns. The logic gate chain includes a plurality of logic gates associated with the columns. Each of the logical gates outputs a logical level to a next-stage logical gate in the series connection. The logic level indicates presence or absence of verify-failure in the associated column. The counter counts the number of output times of the logic level indicating the presence of the verify-failure in a final-stage logic gate of the series connection. A content indicated by the logic level output from each of the logic gates is inverted at a boundary of the logic gate associated with the column having the verify-failure in the logic gate chain.