NAND Flash Read Voltage Calibration via Host IO Monitoring
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Solution Overview
Problem
Existing NAND flash memory systems face challenges in maintaining accurate read voltage thresholds due to stress conditions like Read Disturb and Cross-temperature effects, leading to data errors and performance delays, as current calibration methods fail to effectively address voltage shifts in specific memory areas.
Innovation Solution
The implementation of an optimized read voltage calibration technique that utilizes the physical footprint of host IO operations to selectively sample and calibrate blocks in real-time, focusing on frequently accessed areas to align NAND read voltages with host read IO patterns, thereby reducing error handling triggers and improving read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional calibration methods are used to maintain read voltage thresholds, then voltage accuracy is preserved, but performance delays occur due to ineffective calibration of specific memory areas
Solution Approach 1:
The patent applies local quality by transitioning from global calibration to area-specific calibration. The memory array is divided into multiple areas, and calibration is performed selectively on specific areas based on their individual voltage shift characteristics. This allows each area to be calibrated according to its specific needs rather than applying uniform calibration across the entire memory array, thereby improving voltage accuracy while reducing unnecessary calibration time.
Solution Approach 2:
The patent segments the memory array into multiple distinct areas for independent calibration. By dividing the memory array into smaller calibration zones, the system can identify and calibrate only those areas experiencing voltage threshold shifts. This segmentation enables parallel or selective calibration operations, reducing the overall time required compared to calibrating the entire array uniformly.
2Measurement precision
If comprehensive calibration is performed across all memory areas, then voltage accuracy is improved, but system complexity and calibration overhead increase
Solution Approach 1:
The patent employs preliminary action by performing voltage shift detection before full calibration. The system first scans memory areas to identify which specific areas are experiencing voltage threshold shifts, then only calibrates those identified areas. This preliminary detection step prevents unnecessary calibration operations on areas that do not require it, reducing calibration overhead and simplifying the overall calibration process.
Solution Approach 2:
The patent applies partial action by performing calibration only on the subset of memory areas that require it, rather than calibrating the entire array. The system determines the minimum necessary calibration scope based on detected voltage shifts, applying calibration selectively to affected areas only. This reduces the total calibration operations required while maintaining voltage accuracy where needed.
Data Source
AI summary
Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.