NAND Flash Memory Threshold Voltage Compaction
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Solution Overview
Problem
NAND flash memory devices face capacitive coupling issues between floating gates, leading to non-unique threshold voltage dependencies and increased reading errors, especially in multi-level cells due to the high integration and single pulse erasing methods.
Innovation Solution
The solution involves compacting the distribution of threshold voltages by applying negative voltages to the body region and using multiple limit values to restore and verify the threshold voltages of cells, allowing for controlled erasing and reduced capacitive coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If single pulse erasing is used to erase cells, then erasing speed is improved, but threshold voltage distribution becomes non-uniform due to capacitive coupling effects
Solution Approach 1:
The patent divides the erasing operation into multiple sequential steps instead of using a single pulse. The erasing process is segmented into: (1) applying a first erasing pulse to bring threshold voltages below a reference value, (2) detecting cells that need additional erasing based on threshold voltage detection, and (3) applying a second erasing pulse only to those specific cells. This segmentation allows the process to maintain speed while improving uniformity.
Solution Approach 2:
The patent applies erasing pulses selectively rather than uniformly to all cells. After the initial erasing pulse, only cells whose threshold voltages exceed the reference value receive a second erasing pulse. This partial action approach prevents over-erasing of cells that already meet the criteria while ensuring adequate erasing of cells that need it, thereby improving overall uniformity without sacrificing speed.
2Area of stationary object
If high integration is implemented in NAND memories, then area occupation is reduced, but capacitive coupling effects between adjacent cells increase
Solution Approach 1:
The patent performs preliminary detection of threshold voltages after the first erasing pulse before applying the second pulse. This preliminary action identifies which cells require additional erasing due to capacitive coupling effects from adjacent programmed cells, allowing targeted correction without requiring structural changes that would increase area.
Solution Approach 2:
The patent changes the erasing approach from a fixed single pulse to a multi-stage process with variable pulse application. By monitoring threshold voltage parameters and adjusting the erasing strategy accordingly (applying second pulse only when needed), the system compensates for capacitive coupling effects without altering the physical layout that causes the coupling.
3Quantity of substance
If threshold voltage gap of programmed cells is increased, then storage capacity is improved, but capacitive coupling variation increases
Solution Approach 1:
The patent implements a feedback mechanism where threshold voltages are detected after the first erasing pulse, and this detection information feeds back into the decision of whether to apply a second erasing pulse. This feedback loop allows the system to respond to actual threshold voltage distributions, compensating for variations caused by large gaps in programmed cells and improving reading accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces reading errors and capacitive coupling effects, improving the accuracy and reliability of NAND flash memory devices by compacting the threshold voltage distribution and minimizing the impact of adjacent cell programming.
Implementation Method 1
A problem of the NAND memories is due to the capacitive coupling between the floating gates of adjacent cells; such effect makes the threshold voltage of a cell dependent non-unique on the electric charge stored in its floating gate but even on the electric charges stored in the floating gates of the adjacent cells.
Data Source
AI summary
A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.