NAND Flash Memory System Dynamic Voltage Adjustment
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Solution Overview
Problem
Variations in charge levels within NAND flash memory cells can lead to incorrect data reading due to variations in threshold voltage, which existing storage devices address by encoding data with error correcting codes but struggle with large errors that prevent accurate decoding.
Innovation Solution
A memory system with a nonvolatile memory, encoding, and decoding units that generate and read codewords in parallel, allowing for adjustment of reading voltage to correctly decode data by linking input data to specific bit positions and using error correcting codes to manage errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting codes are used to encode data, then data reliability is improved, but decoding accuracy deteriorates when large errors occur
Solution Approach 1:
The patent divides the decoding process into multiple stages with different reading voltages. The data is first decoded using a standard reading voltage, and if decoding fails, the same data is decoded again using an adjusted reading voltage. This segmentation of the decoding process into multiple attempts with varying parameters allows the system to handle large errors that would otherwise prevent accurate decoding.
Solution Approach 2:
The patent dynamically adjusts the reading voltage based on decoding results. When the decoding unit determines that decoding has failed, the control unit changes the reading voltage applied to the memory cells before attempting decoding again. This dynamic adaptation of operational parameters enables the system to overcome decoding failures caused by charge variations.
2Speed
If a predetermined reading voltage is applied, then reading speed is improved, but data accuracy deteriorates when charge levels vary
Solution Approach 1:
The system maintains a standard reading voltage for normal operations to ensure fast reading speed, but dynamically adjusts the voltage when decoding failures occur. This dynamic approach allows the system to switch between speed-optimized mode and accuracy-optimized mode based on actual decoding results.
Solution Approach 2:
The decoding unit provides feedback to the control unit about decoding success or failure. When decoding fails, this feedback triggers the control unit to adjust the reading voltage and retry the decoding process. This feedback mechanism ensures that data accuracy is maintained without permanently sacrificing reading speed.
3Measurement precision
If reading voltage is adjusted for each bit line, then data accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies different reading voltages to different bit lines based on their specific characteristics. The control unit identifies which bit lines require voltage adjustment and applies the adjusted voltage only to those specific bit lines, rather than uniformly adjusting all bit lines. This localized approach improves data accuracy for problematic bit lines while minimizing the overall complexity increase.
Solution Approach 2:
The system changes the voltage parameter selectively for specific bit lines when decoding failures are detected. Rather than fundamentally changing the device architecture, the patent modifies operational parameters (voltage levels) to achieve improved accuracy, which is a softer form of complexity management.
Data Source
AI summary
According to an embodiment, a memory system includes: a nonvolatile memory to which data in the unit of I/O data of the first number of bits are capable of being input in parallel, and from which data in the unit of I/O data are capable of being output in parallel; a memory interface; an encoding unit configured to generate the second number of codewords; a decoding unit configured to decode a received word read from the nonvolatile memory; and a control unit configured to link an I/O number to the number of the codeword, inputs, to the encoder, each of the codewords of the data to be input to the nonvolatile memory as the data about the position of the bit having the I/O number corresponding to the codeword, reads the second number of received words from the nonvolatile memory to decode the received words, and, when there is a received word that fails to be decoded, reads the received words again after changing the reading voltage, and decodes the received word.