NAND Flash Memory Voltage Control for Data Retention
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Solution Overview
Problem
Conventional NAND flash memory technologies face challenges in data retention and reading accuracy due to threshold shift, leading to increased current consumption and longer charging times, especially when attempting to form threshold distributions in negative regions.
Innovation Solution
A NAND flash memory design where all bit lines are pre-charged and simultaneously read, with a memory cell array comprising p-type wells surrounded by n-type wells, using a row decoder and sense amplifier to control voltages and select memory cells, while charging the source line, n-type well, and p-type well to specific voltages to reduce charge requirements and maintain threshold distribution in both positive and negative regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If threshold distribution is formed in negative region by applying negative potential to word line, then data retention is improved, but current consumption increases and chip fabrication steps increase
Solution Approach 1:
The patent changes the voltage parameter from negative potential to positive potential (VREAD of about 5V) applied to word lines and select gate lines. This parameter change achieves the same threshold distribution formation effect in the negative region without requiring negative potential application, thereby reducing current consumption while maintaining data retention performance.
Solution Approach 2:
Instead of applying negative potential to form threshold distribution in the negative region, the patent inverts the approach by applying positive potential (VREAD) to word lines and select gate lines. This inversion achieves the same effect of forming threshold distribution in the negative region without the harmful side effects of increased current consumption and complex well configuration.
2Reliability
If threshold distribution is formed in negative region by applying negative potential to word line, then data retention is improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the voltage parameter from negative potential to positive potential (VREAD of about 5V) applied to word lines and select gate lines. This parameter change eliminates the need for modified well configurations in the Row decoder part, thereby reducing manufacturing complexity and fabrication steps while maintaining data retention performance.
Solution Approach 2:
The patent inverts the conventional approach of applying negative potential by using positive potential (VREAD) instead. This inversion simplifies the manufacturing process by eliminating the need for complex well configuration modifications in the Row decoder part, making the fabrication process more straightforward.
3Speed
If all bit lines are simultaneously read, then reading speed is improved, but charge requirements and pre-charging time increase
Solution Approach 1:
The patent changes the voltage parameter by applying VREAD (about 5V) to word lines and select gate lines during reading operations. This parameter change enables simultaneous reading of all bit lines while reducing the charge requirements for pre-charging by optimizing the voltage distribution across the memory array, thereby improving reading speed without proportionally increasing charge requirements.
4Ease of operation
If VREAD is applied to all word lines and select gate lines, then reading operation is simplified, but current consumption increases
Solution Approach 1:
The patent applies VREAD (about 5V) to word lines and select gate lines during reading operations, which simplifies the reading operation by eliminating the need for complex voltage sequencing. This parameter change achieves operational simplicity while the optimized voltage application reduces overall current consumption compared to conventional approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the amount of charge required and time needed for pre-charging, while maintaining accurate threshold distribution in both positive and negative regions, thereby improving data retention and reading efficiency without increasing current consumption.
Implementation Method 1
Due to the capacitive coupling, the bit line voltage is affected if the adjacent bit lines voltage is changed during reading.
Implementation Method 2
data is written by applying a high electrical field to the cell to cause trapping of an electron in an oxide film, thereby changing the threshold of the cell
Data Source
AI summary
A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.