NAND Flash Memory Programming Voltage Step-Up

Solution Overview

Problem

NAND flash memory devices face issues with parasitic capacitance coupling between adjacent memory cells, leading to increased threshold voltage distribution and reduced cell current due to string and source resistance, which are exacerbated in multiple level cell arrays.

Innovation Solution

The solution involves incrementing the programming voltage step-up between word lines from the source side to the drain side of the array, with varying increments to minimize interference and resistance effects, allowing for faster programming and tighter threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If parasitic capacitance coupling exists between adjacent memory cells, then memory density can be increased, but threshold voltage distribution becomes wider and cell current decreases

Engineering Contradiction:

Improvememory densityVSAvoidthreshold voltage distribution

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating the programming voltage based on the position of word lines within the memory array. Word lines closer to the source line receive higher programming voltages than those closer to the drain line, creating localized voltage adjustments that compensate for position-dependent parasitic capacitance effects and resistance variations, thereby maintaining uniform threshold voltage distribution across the array.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the programming voltage parameter dynamically based on word line position. By varying the programming voltage from higher values near the source line to lower values near the drain line, the system compensates for the increasing parasitic capacitance coupling and resistance effects that occur as one moves through the array, thus maintaining consistent programming results across all cells.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If string resistance increases due to programmed cells, then programming speed can be maintained, but cell current decreases and threshold voltage increases

Engineering Contradiction:

Improveprogramming speedVSAvoidcell current

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the programming voltage based on the position of word lines within the memory array. Word lines closer to the source line receive higher programming voltages than those closer to the drain line, creating localized voltage adjustments that compensate for position-dependent parasitic capacitance effects and resistance variations, thereby maintaining uniform threshold voltage distribution across the array.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the programming voltage parameter dynamically based on word line position. By varying the programming voltage from higher values near the source line to lower values near the drain line, the system compensates for the increasing parasitic capacitance coupling and resistance effects that occur as one moves through the array, thus maintaining consistent programming results across all cells.

Inventive Principle:

Principle #35Parameter changes

3Ease of operation

If source resistance increases, then programming operation can be simplified, but cell current decreases and threshold voltage increases

Engineering Contradiction:

Improveprogramming operationVSAvoidcell current

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The patent changes the programming voltage parameter dynamically based on word line position. By varying the programming voltage from higher values near the source line to lower values near the drain line, the system compensates for the increasing parasitic capacitance coupling and resistance effects that occur as one moves through the array, thus maintaining consistent programming results across all cells.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in faster programming and tighter threshold voltage distributions, effectively reducing the impact of floating gate-to-floating gate interference and resistance issues, particularly beneficial for multilevel cell arrays.

Implementation Method 1

As NAND flash memory is scaled, parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem. Because of the capacitive coupling, the cells that are adjacent to a cell storing a charge are prone to having their threshold voltages (Vt) raised.

Methodology Applied

Scientific EffectParasitic capacitance coupling: Parasitic Capacitance

Data Source

PatentUS7663930B2Programming a non-volatile memory device

Publication Date: 2010.02.16 MICRON TECHNOLOGY INC

AI summary

A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line.