NAND Flash Memory Voltage Step Width Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory devices face challenges in maintaining data write reliability due to varying write characteristics of memory cells over repeated write/erase cycles, leading to inconsistent program voltage step widths that affect both speed and reliability.
Innovation Solution
The implementation of an initial voltage adjustment function and a step width adjustment function, which dynamically adjust the program voltage's initial value and step width based on the endurance of memory cells, ensuring appropriate voltage settings for both fresh and cycled cells to maintain reliability and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large step width of program voltage is used, then data write speed is improved, but threshold voltage distribution width increases reducing reliability
Solution Approach 1:
The patent implements dynamic adjustment of program voltage step width based on memory cell endurance characteristics. The step width is not fixed but varies according to the number of write/erase cycles the cells have undergone, allowing optimal balance between speed and reliability at different stages of cell life
Solution Approach 2:
The patent changes the program voltage step width parameter according to memory cell endurance state. By adjusting this critical parameter based on cell history, the system optimizes the trade-off between programming speed and threshold voltage distribution control
2Reliability
If a small step width of program voltage is used, then threshold voltage distribution width is reduced improving reliability, but data write speed decreases
Solution Approach 1:
The system dynamically selects program voltage step width based on real-time assessment of memory cell endurance. Fresh cells receive larger step widths for fast programming, while cycled cells receive smaller step widths to maintain reliability
Solution Approach 2:
The program voltage step width parameter is adjusted according to memory cell endurance characteristics, enabling the system to adapt between speed-optimized and reliability-optimized programming modes
3Device complexity
If program voltage settings are not adjusted for endurance, then device complexity is reduced, but threshold voltage distribution width increases reducing reliability
Solution Approach 1:
The patent incorporates feedback mechanisms that monitor memory cell endurance characteristics and use this information to adjust program voltage step width. This closed-loop approach maintains reliability without requiring overly complex voltage control schemes
Solution Approach 2:
The memory system performs self-adjustment of programming parameters based on its own operational history. The controller automatically modifies voltage settings according to detected cell endurance, eliminating the need for external calibration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These adjustments enhance data write reliability by optimizing program voltage settings for memory cells with different endurance levels, reducing the threshold voltage distribution width and maintaining processing time, thus improving overall data storage performance.
Implementation Method 1
data '0' representing the high threshold voltage state in which the floating gate is injected with electrons and data '1' representing the low threshold voltage state in which electrons in the floating gate are discharged
Data Source
AI summary
A non-volatile semiconductor memory device according to an embodiment includes: a data write portion configured to repeat a write loop until data write is complete, the write loop including a program operation of applying a selected word-line with a program voltage necessary for program and a verify operation of applying the selected word-line with a verify voltage necessary for verify, the program voltage being changed for each write loop by a predetermined step width, the data write being performed in units of a page including a plurality of memory cells selected by the selected word-line; and an endurance determination portion configured to determine the endurance of the memory cells of the page, the data write portion supplies the selected word-line with a program voltage of a step width depending on the endurance.