NAND Flash Memory Voltage Sequencing for Trap Site Management
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Solution Overview
Problem
NAND type flash memory devices experience deterioration in memory cell performance due to repeated write and erase operations, leading to inaccurate data writing as a result of charge accumulation layer state changes and trap sites in the gate insulating film.
Innovation Solution
A nonvolatile semiconductor memory device configuration that applies specific voltage sequences during write operations, including lowering the voltage of the selected word line to a ground voltage after applying a program voltage, and then lowering the unselected word line voltage, to release trapped electrons and maintain the threshold voltage distribution, thereby preventing data storage characteristic deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If repeated write and erase operations are performed on memory cells, then data storage capacity and rewriting capability are improved, but memory cell performance deteriorates due to charge accumulation layer state changes and trap sites in the gate insulating film
Solution Approach 1:
The patent applies preliminary action by performing a dummy write operation before the actual write operation. This preliminary write sequence pre-charges the charge accumulation layer and activates relevant conduction paths, ensuring that subsequent write operations can accurately program data without being affected by pre-existing trap sites or incomplete charge states from previous operations. This preliminary preparation maintains reliable data storage even after repeated rewriting cycles.
Solution Approach 2:
The patent implements continuity of useful action through multi-step write sequences and verify operations that continuously monitor and adjust the charge accumulation state. The write operation is divided into multiple pulses with intermediate verify steps, ensuring continuous charging control and preventing incomplete or erroneous programming. This continuous action maintains consistent memory cell behavior across repeated write/erase cycles.
2Speed
If conventional write operations are used, then write speed is maintained, but data writing accuracy deteriorates due to trap sites in the gate insulating film
Solution Approach 1:
The patent segments the write operation into multiple distinct steps: preliminary write sequence, main write sequence with multiple pulses, and verify operations. Each segment serves a specific function - the preliminary segment prepares the charge accumulation layer, the main segment performs actual data programming through controlled pulses, and the verify segment confirms accurate writing. This segmentation enables high write speed while ensuring data writing accuracy by addressing trap site effects at each stage.
Solution Approach 2:
The patent incorporates feedback through verify operations that read back the written data to confirm accurate programming. The verify operation uses read pulses to detect the threshold voltage state of the memory cell and compares it against expected values. This feedback mechanism identifies and corrects writing errors caused by trap sites, maintaining data writing accuracy without significantly reducing write speed.
3Ease of operation
If voltage is applied to unselected word lines during write operation, then memory cell selection is improved, but threshold voltage distribution changes occur due to coupling capacitance effects
Solution Approach 1:
The patent applies local quality by differentiating voltage levels between selected and unselected word lines throughout the write operation sequence. The selected word line receives high voltage pulses to program data, while unselected word lines receive lower voltage levels that prevent unintended programming. This localized voltage control maintains clear memory cell selection while stabilizing the threshold voltage distribution of unselected cells by minimizing their exposure to high voltage stress and coupling capacitance effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate verify operations and maintains favorable data storage characteristics by controlling the threshold voltage distribution and reducing cell current caused by trapped electrons, while enabling efficient electron release from trap sites, thus extending memory cell lifespan.
Implementation Method 1
A memory cell of the NAND type flash memory includes a charge accumulation layer formed on a semiconductor substrate via a tunnel insulating film
Implementation Method 2
lowering the voltage applied to the unselected word line from the second voltage to a third voltage which is smaller than the second voltage, thereby releasing electrons from trap sites
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory cell array including a memory string having plural series-connected memory transistors; plural word lines disposed to be connected to the memory transistor in the memory string; plural bit lines electrically connected to an end of the memory string; and a control circuit. When performing a write operation on the memory cell array, the control circuit applies a first voltage to a selected word line selected from the plural word lines, applies a second voltage smaller than the first voltage to an unselected word line rendered unselected from the word lines. Before lowering a voltage applied to the unselected word line from the second voltage to a third voltage smaller than the second voltage, it lowers a voltage applied to the selected word line from the first voltage to a fourth voltage smaller than the first voltage.