NAND Flash Memory Cell Programming Method for Vt Distribution Tightening
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Solution Overview
Problem
As NAND flash memory scales, parasitic capacitance coupling between adjacent memory cell floating gates leads to wider Vt distributions, degrading programming performance, especially in multi-level cell (MLC) devices where threshold voltage differences are small, causing increased interference and performance issues.
Innovation Solution
A method for programming non-volatile multilevel memory cells involves alternating between programming lower pages and an upper page on even and odd bit lines, with reprogramming of the upper page occurring after adjacent cells have finished their upper page programming, tightening the threshold voltage distributions and reducing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase density, then storage capacity is improved, but parasitic capacitance coupling between adjacent floating gates increases causing wider Vt distributions
Solution Approach 1:
The patent segments the programming operation into multiple phases: programming lower pages first, then programming upper pages only after adjacent cells have completed their upper page programming. This temporal segmentation prevents simultaneous charge injection into adjacent floating gates, thereby reducing parasitic capacitance coupling effects and tightening Vt distributions while maintaining high-density scaled architecture
Solution Approach 2:
The patent performs preliminary programming of lower pages before proceeding to upper page programming. By completing lower page programming first and verifying it, the system ensures that when upper pages are programmed, the lower pages are already stable and won't be affected by charge injection during upper page programming, thus preventing Vt distribution widening in scaled cells
2Quantity of substance
If multiple level cell (MLC) programming is implemented to increase bits per cell, then storage density is improved, but floating gate-to-floating gate interference increases causing degraded programming performance
Solution Approach 1:
The patent divides MLC programming into separate lower page and upper page operations executed at different times. Lower pages are programmed and verified first, then upper pages are programmed after adjacent cells have completed their upper page programming. This temporal separation prevents charge injection interference between adjacent floating gates during MLC programming, maintaining reliability while achieving high storage density
Solution Approach 2:
The patent uses verification operations as an intermediary step between lower page and upper page programming. The verification process checks that lower pages are properly programmed and stable before proceeding to upper page programming, acting as a mediator that ensures no interference occurs between the two programming operations in MLC cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the programming performance by tightening the threshold voltage distributions, enhancing the reliability and accuracy of data storage in MLC NAND arrays by minimizing floating gate-to-floating gate interference.
Implementation Method 1
parasitic capacitance coupling between adjacent memory cell floating gates becomes a problem
Data Source
AI summary
The present disclosure includes methods, devices, modules, and systems for programming multilevel non-volatile memory cells, each cell having a number of lower pages and an upper page. One method includes programming a first lower page, programming a second lower page, programming a third lower page, programming an upper page, and reprogramming the upper page of a cell.