NAND Flash Wear-Leveling via Erase Time Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory systems face challenges in maintaining data retention characteristics due to the degradation of gate oxide films from repeated rewrite operations, leading to shorter service life and unbalanced erase processes.
Innovation Solution
A memory system comprising a nonvolatile memory with blocks as data erase units, a measuring unit to track erase times, and a block controller that writes data into the oldest free block with the minimum erase count, ensuring balanced erase operations and extended service life.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is sequentially recorded in addresses specified from the exterior, then data writing is simple and fast, but erase processes become concentrated in specified regions leading to unbalanced wear and shorter service life
Solution Approach 1:
The patent introduces a wear-leveling management unit as an intermediary between the host and the NAND flash memory. This unit intercepts write commands, translates logical addresses to physical addresses, and redistributes data across different blocks. By doing so, it prevents direct sequential writing that causes wear concentration, while maintaining simple host interface operations.
Solution Approach 2:
The patent changes the addressing parameter from direct sequential addressing to indirect addressing through a translation layer. The wear-leveling management unit maintains a mapping table that translates host-provided logical addresses to optimized physical addresses, transforming the write operation from a simple sequential process into a distributed write pattern that balances erase operations across blocks.
2Reliability
If erase processes are performed frequently to maintain data integrity, then data retention is improved, but the gate oxide film degrades faster and service life shortens
Solution Approach 1:
The patent performs preliminary wear-leveling actions by predicting which blocks will need erasing soon and proactively distributing data to blocks with lower erase counts before the erase actually occurs. The wear-leveling management unit monitors block erase counts and preemptively redirects writes to extend the interval between erases for any given block, thereby reducing cumulative wear while maintaining data integrity.
Solution Approach 2:
The patent implements a cushioning mechanism by maintaining a buffer of unused blocks and distributing writes across multiple blocks simultaneously. This creates a time buffer that allows erase operations to be spread out over longer periods, cushioning the impact of frequent erases on any single block's gate oxide film and extending overall service life.
3Reliability
If the interval between erase processes is shortened to improve data retention, then rewrite capability is maintained, but gate oxide film degradation accelerates and service life reduces
Solution Approach 1:
The patent segments the write operations across multiple blocks rather than concentrating them in one block. The wear-leveling management unit divides incoming data streams and distributes them to different physical blocks, ensuring that no single block experiences frequent sequential erases. This segmentation maintains rewrite capability across the memory system while reducing the erase frequency burden on individual blocks, thereby extending service life.
Data Source
AI summary
A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.