NAND Flash Memory Wear Leveling via Segmented Management Tables
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Solution Overview
Problem
The existing memory systems face challenges in managing the large size of management tables required for NAND flash memory, which increases with capacity, leading to slower address translation and reduced retention characteristics due to frequent rewriting, necessitating a method to reduce management table capacity and enhance wear leveling.
Innovation Solution
A memory system with parallel operation elements and a controller that manages erasing operations in logical block units, reducing the size of management tables and improving wear leveling by distributing data updates evenly across physical blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the unit of data management is set to a small size (e.g., page size) to improve address translation precision, then the size of management tables increases, but this causes the management tables to not fit in the main memory of the controller and reduces address translation speed
Solution Approach 1:
The patent segments the management table into two parts: a first management table that fits in the controller's main memory for fast address translation, and a second management table stored in the nonvolatile semiconductor memory for complete address mapping. This segmentation allows the system to maintain both high translation speed (via the small first table) and complete address precision (via the comprehensive second table).
Solution Approach 2:
The patent extracts the most frequently accessed management information into a separate first management table that resides in the controller's main memory, while keeping the complete management data in the second table in the nonvolatile memory. This extraction allows the controller to perform common address translations without accessing the large second table, thereby improving speed while maintaining precision when needed.
2Reliability
If wear leveling processing is performed to equally distribute data update sections and improve reliability, then the management table size increases, but this causes the management table to not fit in the main memory of the controller
Solution Approach 1:
The patent segments the wear leveling management functionality into two parts: a first wear leveling management table in the controller's main memory that tracks only the necessary wear leveling information for active blocks, and a second wear leveling management table in the nonvolatile memory that stores complete wear leveling data. This segmentation reduces the memory burden on the controller while maintaining wear leveling reliability.
Solution Approach 2:
The patent extracts the essential wear leveling control information into a separate first management table in the controller, removing the need to store the entire wear leveling data structure in the controller's limited memory. This extraction allows the controller to perform wear leveling operations with reduced memory complexity while maintaining reliability.
3Manufacturing precision
If the number of times of erasing is managed in physical block units to improve manufacturing precision, then the management table size increases, but this is against the reduction in the management table size
Solution Approach 1:
The patent segments the erasing count management into two levels: a first management table in the controller that stores erasing counts only for logical blocks currently in use or recently accessed, and a second management table in the nonvolatile memory that stores the complete erasing count history for all physical blocks. This segmentation enables precise tracking of erasing counts while keeping the controller's management table size small.
Solution Approach 2:
The patent extracts the detailed erasing count information for physical blocks into the second management table in the nonvolatile memory, leaving only the essential erasing count data for active logical blocks in the controller's first management table. This extraction reduces the management table size in the controller while maintaining precise erasing count tracking capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the memory required for management tables, enhances data retention by evenly distributing write operations, and improves the durability of NAND flash memory by minimizing the deterioration of gate oxide films.
Implementation Method 1
wear leveling processing, for example, a logical address designated by the host apparatus is translated into a physical address of the nonvolatile semiconductor memory in which the data update sections are equally distributed
Implementation Method 2
In writing and erasing of data in the NAND flash memory, electrons are injected in and discharged from a floating gate by applying high voltage between a substrate and a control gate
Data Source
AI summary
A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.