NAND Flash Word Line Isolation for Lateral Field Suppression
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Solution Overview
Problem
In NAND flash memory systems, high lateral electric fields during programming lead to program disturb, especially when scaling down memory cells, causing unintended threshold voltage shifts and data corruption.
Innovation Solution
The solution involves increasing the distance between the isolation word line and the selected word line as a function of the distance from the drain side select gate, allowing for reduced vertical and lateral electric fields by adjusting the number of word lines separating them, thereby minimizing program disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are scaled down to increase storage density, then storage capacity per area is improved, but high lateral electric fields are generated causing program disturb
Solution Approach 1:
The patent applies different voltages to different word lines based on their position relative to the selected word line. Specifically, word lines closer to the selected word line receive higher voltages to suppress lateral electric fields, while distant word lines receive lower voltages. This localized voltage adjustment targets the specific region where high electric fields cause program disturb, resolving the contradiction between scaling for density and preventing program disturb.
2Object-affected harmful factors
If isolation voltage is applied to suppress lateral electric fields, then program disturb is reduced, but channel capacitance may be insufficient when selected word line is close to drain select gate
Solution Approach 1:
The patent dynamically adjusts the isolation voltage based on the position of the selected word line. When the selected word line is close to the drain select gate, the isolation voltage is increased to maintain adequate channel capacitance and prevent program disturb. When the selected word line is far from the drain select gate, the isolation voltage is reduced. This dynamic adjustment resolves the contradiction between suppressing lateral electric fields and maintaining channel capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses high electric fields and reduces program disturb by maintaining adequate channel capacitance and voltage distribution, even as memory cells are scaled down.
Implementation Method 1
The control gate lines (CG) are typically formed over the floating gates as a self-aligned stack, and are capacitively coupled with each other through an intermediate dielectric layer 19
Implementation Method 2
When programming a NAND flash memory cell, a program voltage is applied to the control gate and the channel area of the NAND string that is selected for programming is grounded
Implementation Method 3
Electrons from the channel area under the NAND string are injected into the floating gate
Data Source
AI summary
In an improved EASB programming scheme for a flash device (e.g. a NAND flash device), the number of word lines separating a selected word line (to which a program voltage is applied) and an isolation word line (to which an isolation voltage is applied) is adjusted as a function (e.g. inverse function) of distance of the selected word line from the drain side select gate to reduce program disturb due to high vertical and lateral electric fields at or near the isolation transistor when programming word lines closer to the drain side select gate. The selected and isolation word lines are preferably separated by two or more word lines to which intermediate voltage(s) are applied.