NAND Flash Word-Line Layout for Reliable Voltage Transfer
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Solution Overview
Problem
In miniaturized NAND flash memories, the local self-boost method used for writing data leads to a decrease in the voltage transfer capability of MOS transistors, which can result in erroneous programming due to insufficient voltage transfer to the word lines.
Innovation Solution
The semiconductor memory device configuration includes a specific arrangement of metal wiring layers above the gate electrodes of MOS transistors, where M number of word lines close to the selected word line pass through a region above the gate electrode without passing over the impurity diffused layers, thereby preventing depletion and maintaining voltage transfer capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the local self-boost method is used for writing data in miniaturized NAND flash memories, then data writing capability is improved, but the voltage transfer capability of MOS transistors decreases
Solution Approach 1:
The patent introduces a new spatial dimension for routing word lines by passing them through the region above gate electrodes rather than over impurity diffused layers. This dimensional change in wiring layout allows simultaneous achievement of local self-boost for data writing and adequate voltage transfer to word lines, resolving the contradiction between writing capability and voltage transfer reliability
2Adaptability or versatility
If metal wiring layers pass over impurity diffused layers of MOS transistors, then routing flexibility is improved, but depletion of impurity diffused layers occurs causing insufficient voltage transfer
Solution Approach 1:
The patent segments the routing paths for different word lines. Specifically, word lines adjacent to the selected word line are routed through the region above gate electrodes, while other word lines can be routed over impurity diffused layers. This segmentation allows selective optimization of voltage transfer for critical word lines while maintaining overall routing flexibility
Solution Approach 2:
The patent applies different routing strategies to different word lines based on their specific requirements. Word lines that require adequate voltage transfer (those adjacent to the selected word line) are routed through the region above gate electrodes, while other word lines can use conventional routing over impurity diffused layers. This local differentiation resolves the contradiction by applying the appropriate routing method to each specific case
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents the depletion of impurity diffused layers in MOS transistors, thereby maintaining the voltage transfer capability and ensuring reliable operation of the NAND flash memory by preventing erroneous programming.
Implementation Method 1
gate insulating films interposed therebetween
Implementation Method 2
M number of metal wiring layers 101 are arranged above the gate electrode 100 in this region
Implementation Method 3
two impurity diffused layers 112 which are formed at the surface of one of the element regions
Data Source
AI summary
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.