NAND Flash Word Line Voltage Control for Program Erase Speed Consistency
Solution Overview
Problem
Conventional NAND flash memories face challenges in achieving uniform programming and erasing speeds due to varying coupling ratios between memory cells and select transistors, leading to inconsistent floating gate voltages and differing program/erase speeds across word lines.
Innovation Solution
The implementation of a non-volatile memory device that divides word lines into groups based on adjacency to string or ground select lines, with specific verify voltage levels applied to each group to adjust programming and erasing operations, allowing for differentiated voltage levels to optimize program and erase speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional NAND flash memory uses uniform word line voltages for all word lines, then device complexity is reduced, but programming and erasing speeds become inconsistent across different word lines
Solution Approach 1:
The patent divides word lines into multiple groups (first group adjacent to select lines, second group not adjacent) and applies different verify voltages to each group. This segmentation resolves the contradiction by enabling differentiated voltage control for different word line positions, improving program/erase speed consistency without requiring completely individualized control of each word line.
Solution Approach 2:
The patent applies different verify voltage levels to different groups of word lines based on their local characteristics (adjacency to select lines). Word lines in the first group receive different verify voltages than word lines in the second group, allowing each local region to be optimized for its specific coupling ratio characteristics, thereby improving overall speed consistency.
2Productivity
If different verify voltages are applied to different word line groups, then program and erase speed consistency is improved, but device complexity increases
Solution Approach 1:
By segmenting word lines into a limited number of groups (first group and second group) rather than treating each word line individually, the patent achieves speed consistency improvement while controlling the increase in device complexity. The segmentation strategy balances performance improvement with manageable control complexity.
Solution Approach 2:
The patent uses a unified voltage control architecture that can selectively apply different verify voltages to different word line groups based on their position. This multi-functional voltage control system handles both groups using the same control mechanism, reducing the overall complexity increase compared to fully individualized control.
3Speed
If higher verify voltages are applied to word lines adjacent to select lines, then programming speed of these word lines is improved, but power consumption increases
Solution Approach 1:
The patent applies higher verify voltages only to word lines in the first group (adjacent to select lines) that have different coupling ratio characteristics, while using standard verify voltages for word lines in the second group. This localized voltage enhancement improves programming speed where needed without unnecessarily increasing power consumption across the entire memory array.
Solution Approach 2:
The patent changes the verify voltage parameter selectively for different word line groups based on their operational characteristics. By adjusting the verify voltage parameter only for word lines that require it (first group), the patent optimizes programming speed for problematic word lines while minimizing overall power consumption increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances program and erase speeds by applying tailored verify voltages to word lines based on their position, resulting in improved operational efficiency and consistent cell state margins.
Implementation Method 1
a memory cell of a conventional NAND flash memory utilizes Fowler-Nordheim (F-N) tunneling current to program and erase data
Implementation Method 2
A dielectric layer having an oxide/nitride/oxide (ONO) structure with a relatively high storage capacity may be formed between the control gate CG and the floating gate FG
Data Source
AI summary
Non-volatile memory devices and operating methods thereof are provided. In an operating method, a first operation is performed by applying a first voltage to at least one word line. The first operation includes one of a programming or erasing operation. The first operation is verified by applying a verify voltage to each of the at least one word lines. The voltage level of each verify voltage is determined according to position information of a corresponding one of the at least one word lines.