NAND Flash Word Line Layout to Preserve MOS Voltage Transfer
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Solution Overview
Problem
In miniaturized NAND flash memories, the local self-boost method for writing data leads to a decrease in the voltage transfer capability of MOS transistors, affecting the reliability of data writing operations.
Innovation Solution
The semiconductor memory device configuration includes an arrangement where metal wiring layers connected to word lines pass through a region above the gate electrode of MOS transistors without passing over the impurity diffused layers, thereby preventing depletion of the impurity diffused layers and maintaining voltage transfer capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wiring layers pass over impurity diffused layers to connect word lines, then electrical connection is achieved, but impurity diffused layers become depleted and voltage transfer capability decreases
Solution Approach 1:
The harmful interaction between metal wiring layers and impurity diffused layers is extracted by separating their spatial paths. The metal wiring layers are routed to pass through regions above gate electrodes rather than over impurity diffused layers, eliminating the depletion effect while maintaining electrical connectivity through alternative pathways.
Solution Approach 2:
Gate electrode regions serve as intermediary zones that allow metal wiring layers to pass through without directly contacting impurity diffused layers. This intermediary routing path enables electrical connection while preventing the harmful depletion effect that would occur with direct contact.
2Productivity
If miniaturization is implemented to increase integration, then device capacity increases, but voltage transfer capability of MOS transistors decreases due to local self-boost method
Solution Approach 1:
The harmful depletion effect is extracted and removed from the miniaturized device structure by rerouting metal wiring layers. This allows the device to maintain high integration benefits while eliminating the voltage transfer degradation that would otherwise accompany miniaturization.
Solution Approach 2:
Different regions of the device are assigned different functions: gate electrode regions serve as transmission corridors for metal wiring layers, while impurity diffused layer regions are protected from depletion. This local differentiation of quality and function enables both miniaturization and maintained voltage transfer capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the decrease in voltage transfer capability of MOS transistors, enhancing the operation reliability of NAND flash memories by preventing impurity diffused layer depletion.
Implementation Method 1
an (N+1) number of first transistors which are formed on (N+1) number of element regions provided in a semiconductor substrate, include gate electrodes formed above the element regions with gate insulating films interposed therebetween, and transfer the voltage to the word lines respectively
Implementation Method 2
gate electrodes formed above the element regions with gate insulating films interposed therebetween
Implementation Method 3
pass through a region above the gate electrode of MOS transistors without passing over the impurity diffused layers, thereby preventing depletion of the impurity diffused layers
Data Source
AI summary
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i−th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i−th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.