NAND Flash Memory Writability Determination Circuit

The patent applies preliminary action by writing a determination flag to the memory cell array before performing the actual data write operation. This flag indicates whether the memory page is suitable for writing based on predetermined criteria such as read disturb stress history. By assessing writability in advance, the system prevents abnormal write errors caused by power shutdown or read disturb stress, thereby improving write reliability without significantly impacting write efficiency since the determination process is integrated into the existing write workflow

The patent merges the write determination function with the existing controller and memory cell array structure. The control circuit integrates the determination logic that assesses whether a memory page is suitable for writing by evaluating factors like read disturb stress, and this determination is performed using the same hardware resources already present in the NAND flash memory system. This approach improves write determination accuracy while avoiding significant increases in device complexity, as no separate dedicated determination hardware is introduced

The patent implements self-service by enabling the memory system to automatically assess its own writability status through the determination flag mechanism. The control circuit monitors conditions such as read disturb stress and power shutdown history, and autonomously determines whether a write operation should proceed. This self-assessment capability improves data management reliability by preventing abnormal writes while maintaining write throughput, as the determination process is seamlessly integrated into the normal write operation flow without requiring external intervention or complex additional procedures