NAND Flash Memory Write Control for Hot Electron Disturbance
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Solution Overview
Problem
In NAND type flash memory, as memory cells are miniaturized, the reduced distance between select gate transistors and adjacent memory cells leads to incorrect writes due to hot electrons being injected into non-selected cells, causing a phenomenon known as the 'programming disturbance' or 'wrong write' due to interband tunnel currents.
Innovation Solution
A nonvolatile semiconductor memory system that adjusts write conditions based on the position of the selected cell relative to the select gate transistors, including altering the timing and duration of the write potential applied to the selected word line, to reduce hot electron generation and injection into non-selected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase memory capacity, then the memory capacity is improved, but the distance between select gate transistors and adjacent memory cells is reduced, causing hot electrons to be injected into non-selected cells
Solution Approach 1:
The patent applies different write conditions to memory cells based on their local position relative to select gate transistors. Specifically, when a memory cell adjacent to a select gate transistor is selected for write, the write potential is applied for a shorter duration or with modified timing compared to when a non-adjacent cell is selected. This local differentiation prevents hot electron injection into non-selected cells while maintaining write capability for selected cells, thus resolving the contradiction between miniaturization and harmful hot electron effects.
2Manufacturing precision
If the distance between select gate transistor and adjacent memory cell is reduced, then the memory cell density is improved, but wrong writes occur due to hot electrons reaching the memory cell without losing much energy
Solution Approach 1:
The patent dynamically adjusts write conditions based on the position of the selected memory cell. When a memory cell adjacent to a select gate transistor is detected as the selected cell, the write control circuit modifies the write operation by applying the write potential for a shorter time period or with different timing characteristics. This dynamic adaptation prevents hot electrons from being injected into non-selected cells during miniaturized device operation, thereby maintaining write accuracy while preserving high cell density.
3Speed
If conventional write conditions are used for miniaturized memory cells, then the write operation speed is maintained, but programming disturbance occurs due to interband tunnel currents generating hot electrons
Solution Approach 1:
The patent changes the temporal parameters of the write operation based on the selected cell's position. When a memory cell adjacent to a select gate transistor is selected, the write potential application duration is reduced or the timing is adjusted to minimize the generation of hot electrons through interband tunnel currents. This parameter modification prevents programming disturbance while maintaining acceptable write speeds for miniaturized memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents wrong writes by controlling the write conditions to suppress hot electron injection into non-selected cells, improving memory cell characteristics and reducing threshold fluctuations, thereby enhancing the reliability and accuracy of write operations.
Implementation Method 1
a high electric field is generated in a tunnel insulating film between the channel of the selected cell and the floating gate electrode, and electrons are injected in the floating gate electrode of the selected cell by FN (Fowler-Nordheim) tunneling phenomenon
Implementation Method 2
a current based on an interband tunnel flow between a semiconductor substrate (well region) and a diffusion layer of the select gate transistor due to an increase in the channel potential. The current generates hot electrons
Data Source
AI summary
A nonvolatile semiconductor memory according to examples of the present invention includes a NAND string comprised memory cells connected in series, two select gate transistors each of which is connected to each end of the NAND string, and a write control circuit which makes a first write condition for a selected cell different from a second write condition for the selected cell. The first write condition is that the selected cell is one of two memory cells adjacent to the two select gate transistors. The second write condition is that the selected cell is one of the memory cells except for two memory cells adjacent to the two select gate transistors.