NAND Flash Memory Write Loop Voltage Control
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Solution Overview
Problem
In NAND type FLASH memory, excessively increasing the Quick Pass Write (QPW) voltage leads to an increase in the number of programming loops required to reach the desired threshold voltage of memory cell transistors, thereby prolonging the data write operation time.
Innovation Solution
A semiconductor memory device that includes a control circuit to execute write operations in multiple loops, where the program voltage is increased for each subsequent loop, and the control circuit selects a pass write voltage for the bit line based on the sequential position of the loop, allowing for a flexible application of the pass write effect to narrow the threshold voltage distribution without increasing the total write time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the QPW voltage is increased to narrow the threshold voltage distribution, then the width of the threshold voltage distribution is reduced, but the number of programming loops increases and write operation time is prolonged
Solution Approach 1:
The patent segments the write operation into multiple loops with different QPW voltage levels. In earlier loops, a first QPW voltage is applied to begin narrowing the threshold voltage distribution. In later loops, a second QPW voltage (different from the first) is applied to continue narrowing while preventing excessive programming loops. This segmentation allows the system to achieve the desired threshold voltage distribution width without unnecessarily increasing total write time.
Solution Approach 2:
The patent dynamically adjusts the QPW voltage based on the loop sequence and threshold voltage distribution characteristics. The QPW voltage is not fixed but changes throughout the write operation - using a first voltage level in initial loops and a second voltage level in subsequent loops. This dynamic adjustment optimizes the balance between narrowing the threshold voltage distribution and minimizing the number of programming loops required.
2Manufacturing precision
If the QPW voltage is excessively increased to narrow the threshold voltage distribution, then the threshold voltage distribution width is reduced, but the number of programming loops increases
Solution Approach 1:
The write operation is divided into multiple segments or loops, each using appropriately tuned QPW voltage levels. Rather than applying a single high QPW voltage that causes excessive loops, the patent uses multiple loops with modulated voltage levels - a first QPW voltage in earlier loops and a second QPW voltage in later loops - to achieve the desired threshold voltage distribution width while maintaining programming efficiency.
Solution Approach 2:
The patent changes the QPW voltage parameter throughout the write operation based on the loop sequence and observed threshold voltage distribution characteristics. By adjusting the QPW voltage level dynamically - using a first voltage level initially and transitioning to a second voltage level - the system optimizes both the narrowing of threshold voltage distribution and the efficiency of the programming process, avoiding excessive loops.
Data Source
AI summary
A semiconductor memory device includes a word line connected to memory cells, bit lines respectively connected to the memory cells, and a control circuit configured to control voltages applied to the word line and the bit lines during a write operation. When writing data into a target memory cell, the control circuit executes first and second loops in sequence. In executing the first loop, the control circuit applies a first program voltage to the word line during the program operation, and applies a verify voltage to the word line during the verify operation, and upon detecting that the verify operation neither passed nor failed, the control circuit selects one of two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to a sequential position of the first loop in the sequence of loops.