NAND Flash Write Ratio Control for Speed and Endurance

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Solution Overview

Problem

NAND flash memory systems face a trade-off between data write speed and capacity, with mechanisms like SLC buffers increasing write speed but reducing lifespan and requiring additional migration processes, leading to inefficiencies and potential write cycle life reduction.

Innovation Solution

A memory system with a controller that manages multiple write types (e.g., SLC and TLC) based on performance levels or ratios specified by the host, optimizing write speed and reducing unnecessary migrations to extend lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SLC buffer is used to improve write speed, then write speed is improved, but write cycle life is reduced

Engineering Contradiction:

Improvewrite speedVSAvoidwrite cycle life

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent changes the write type parameters (SLC/TLC ratios) based on performance levels to optimize both write speed and write cycle life. By dynamically adjusting the mix of SLC and TLC writes rather than always using SLC buffer, the system achieves high write speeds while reducing unnecessary writes to SLC, thereby extending write cycle life.

Inventive Principle:

Principle #35Parameter changes

2Speed

If SLC buffer is used to improve write speed, then write speed is improved, but device complexity increases due to migration processes

Engineering Contradiction:

Improvewrite speedVSAvoidmigration process complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by determining the performance level and calculating appropriate SLC/TLC write ratios before actual writing occurs. This upfront planning reduces the need for complex migration processes later, as the write strategy is optimized in advance based on expected performance requirements.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The controller acts as an intermediary that manages the complexity of coordinating SLC and TLC writes. By centralizing the logic for determining write ratios and managing the write pool allocation in the controller, the patent reduces the complexity burden on the overall system architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If Foggy-Fine method is used to write data, then amount of data written is increased, but write speed is reduced

Engineering Contradiction:

Improveamount of data writtenVSAvoidwrite speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The patent dynamically adjusts the write strategy by mixing SLC and TLC writes based on performance levels rather than using a fixed Foggy-Fine approach. This dynamic allocation allows the system to achieve both high data throughput and maintained write speeds by adapting the write mix to current performance requirements.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20260064316A1Memory system

Publication Date: 2026.03.05 KIOXIA CORP

AI summary

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller is connectable to a host, and is configured to control the nonvolatile memory. The controller is configured to write data to the nonvolatile memory using a plurality of write types with different data write speeds based on information provided by the host, and determine a write ratio of the plurality of the write types.