NAND Flash Two-Stage Write Control for Data Reliability

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Solution Overview

Problem

Existing memory systems face challenges in achieving high performance and reliability, particularly in the management and writing of data to non-volatile memory devices like NAND flash, which can be affected by factors such as data reliability over time and operational conditions.

Innovation Solution

A memory system with a non-volatile memory and a memory controller that performs a two-stage write operation, where the first write operation writes n bits of data and a second write operation writes additional m bits, with the selection of data load methods for the second write operation based on the reliability index of the first write data, using internal or external data loading depending on the reliability of the stored data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single data load method is used for all write operations, then the device complexity is reduced, but the write performance and reliability cannot be optimized under different conditions

Engineering Contradiction:
Improvewrite performanceVSAvoiddata load method selection complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements dynamic selection of data load methods based on real-time conditions. The memory controller dynamically chooses between different data load methods (first data load method or second data load method) according to the elapsed time since the last write operation to the same memory location, allowing the system to adapt to changing conditions and optimize write performance without excessive complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of data load method selection based on the elapsed time parameter. When the elapsed time exceeds a predetermined threshold, one data load method is selected; when it is within the threshold, another method is selected. This parameter-based selection mechanism enables performance optimization while maintaining manageable system complexity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If data is written without considering elapsed time or reliability indices, then the write speed is increased, but data integrity and reliability deteriorate

Engineering Contradiction:
Improvedata integrityVSAvoidwrite operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements a feedback mechanism where the memory controller monitors the elapsed time since the last write operation to the same memory location and uses this information to select the appropriate data load method. This feedback loop ensures that data integrity is maintained by adapting the write operation to the current state of the memory, preventing reliability degradation while minimizing time loss through intelligent method selection

Inventive Principle:
Principle #23Feedback

3Reliability

If the memory controller always uses the most reliable data load method, then data reliability is improved, but the write performance decreases due to method selection overhead

Engineering Contradiction:
Improvedata reliabilityVSAvoidwrite throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the data load method parameter based on the elapsed time parameter. By setting a predetermined time threshold, the system automatically switches between different data load methods without requiring complex real-time analysis. This approach maintains high data reliability through appropriate method selection while minimizing performance overhead by using a simple time-based decision criterion

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12613661B2Memory system and memory device
Publication Date: 2026.04.28 KIOXIA CORP
  • US12613661B2 patent drawing
  • US12613661B2 patent drawing
  • US12613661B2 patent drawing

AI summary

A memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a memory cell and a control circuit that writes first data of n bits to the memory cell by a first write operation and writes second data of m bits, which includes the n bits of the first data, to the memory cell by a second write operation. The memory controller issues a first command sequence to the non-volatile memory to execute the first write operation, selects one of first and second methods for preparing the second data for the second write operation based on an index related to reliability of the first data stored in the memory cell, and issues a second command sequence to the non-volatile memory to execute the second write operation, the second command sequence indicating the selected method for preparing the second data.