NAND Flash Memory Write Sequence for Interference Reduction
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Solution Overview
Problem
The continuous reduction of cell spacing in NAND flash memory devices to improve storage density leads to increased interference between adjacent memory cells, compromising the reliability of the memory device.
Innovation Solution
An operation method for a NAND flash memory device that involves performing batch writing to each cell page, grouping memory cells as either earlier or later written based on connected bit lines, and applying a specific write sequence where each cell page is identical to one of its nearest neighbors but opposite to the other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cell spacing is continuously reduced to improve storage density, then storage density is improved, but interference between adjacent memory cells increases and reliability deteriorates
Solution Approach 1:
The patent segments the write operation into different phases and groups memory cells into different write sequences based on their bit line connections. By dividing the write operations into multiple sequences and applying them differently to adjacent cell pages, the patent reduces the concentration of interference in any single location, thereby maintaining reliability while achieving high storage density
Solution Approach 2:
The patent applies different write sequences to different cell pages based on their local characteristics (even-numbered vs. odd-numbered bit lines). This local differentiation ensures that high cross-coupling memory cells are evenly distributed across the memory array, preventing localized interference accumulation and improving overall reliability without sacrificing storage density
2Reliability
If batch writing is performed with specific write sequences to reduce interference, then reliability is improved, but operation complexity increases
Solution Approach 1:
The patent introduces asymmetry in the write sequence assignment by using different sequences (first write sequence for even-numbered bit lines, second write sequence for odd-numbered bit lines) for adjacent cell pages. This asymmetric approach effectively distributes high cross-coupling memory cells and reduces interference, improving read accuracy while the systematic nature of the asymmetry keeps the complexity manageable
Solution Approach 2:
The patent employs periodic alternation between different write sequences for adjacent cell pages. This periodic pattern (even bit lines use one sequence, odd bit lines use another) creates a regular, predictable structure that reduces interference through systematic distribution of write operations, making the complexity easier to manage through pattern recognition
Data Source
AI summary
An operation method for a memory device is provided. A memory block of the memory device includes an array of memory cells including cell strings and cell pages. Serially numbered and arranged bit lines are connected to the cell strings, respectively. Serially numbered and arranged word lines are connected to the cell pages, respectively. The operation method includes: performing a batch writing to each of the cell pages, such that the memory cells in each cell page are respectively grouped as an earlier written memory cell or a later written memory cell, depending on the connected bit line is either even-numbered or odd-numbered. Each cell page has a respective write sequence. In terms of write sequence, each cell page is identical with one of 2 nearest cell pages, and opposite to the other of the 2 nearest cell pages.