NAND Flash Write Sequencing for Threshold Voltage Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
NAND flash memory systems face challenges in maintaining data reliability due to initial drop and parasitic capacitance effects during write operations, leading to deviations in threshold voltage distributions and reduced data integrity.
Innovation Solution
The implementation of a 1-2-4-8 code for data assignment in NAND flash memory systems, where 4-bit data is written in two separate write operations, with the first operation writing lower and middle bits and the second operation writing upper bits, while also using internal data load (IDL) to restore data and reduce the impact of initial drop and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written in a single operation to improve productivity, then write speed increases, but threshold voltage distribution spread increases due to initial drop and parasitic capacitance effects, worsening data reliability
Solution Approach 1:
The write operation is divided into two separate operations: a first write operation that writes initial data, and a second write operation that writes corrected data after compensating for initial drop and parasitic capacitance effects. This segmentation allows each operation to be optimized independently, maintaining high productivity while improving reliability through error correction in the second operation.
Solution Approach 2:
The patent applies preliminary compensation actions before the final write operation. By predicting and compensating for initial drop and parasitic capacitance effects in advance, the system prepares corrected data that accounts for these phenomena, thereby improving data reliability while maintaining efficient write operations.
2Reliability
If multiple write operations are used to improve data reliability, then threshold voltage distribution spread is reduced, but write time increases, worsening productivity
Solution Approach 1:
The system performs self-correction by automatically detecting and compensating for initial drop and parasitic capacitance effects within the write process itself. The controller calculates compensation values based on the stored data and applies corrections in the second write operation, enabling the system to maintain high reliability without requiring external intervention or excessive additional operations.
3Reliability
If compensation for initial drop and parasitic capacitance is applied to improve data reliability, then threshold voltage accuracy improves, but processing complexity increases, worsening ease of manufacture
Solution Approach 1:
The patent changes the parameter representation of data by storing and processing compensation values that account for initial drop and parasitic capacitance effects. By transforming the data into a compensated form and using modified write operations, the system achieves higher threshold voltage accuracy while managing complexity through systematic parameter transformation rather than complex hardware modifications.
Data Source
AI summary
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.