NAND Flash Memory Write Verification Strategy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND-type flash memory, the reduction in memory string size has led to increased inter-cell interference, resulting in a higher possibility of erroneous data writing during data storage.
Innovation Solution
A semiconductor memory device with a memory cell array that performs a first write operation to form a middle threshold voltage distribution and a second write operation to form threshold voltage distributions corresponding to n bits of data, with a control circuit that verifies the write operation only after the first step, reducing inter-cell interference and enhancing data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory string size is reduced to increase storage capacity, then the storage density is improved, but the inter-cell interference increases causing higher error rate
Solution Approach 1:
The write operation is divided into two distinct phases: a first write operation that forms an initial threshold voltage distribution, and a second write operation that forms the final threshold voltage distribution. This segmentation allows the system to manage inter-cell interference by controlling the program voltage application in separate steps, thereby maintaining data writing accuracy while using reduced memory string sizes for higher storage capacity.
Solution Approach 2:
The first write operation is performed as a preliminary action before the second write operation. This preliminary write establishes an intermediate threshold voltage distribution that prepares the memory cells for the final write operation, reducing the impact of inter-cell interference during the critical final programming stage while enabling high-density storage.
2Ease of operation
If a single write operation is performed to simplify the writing process, then the operation complexity is reduced, but the data writing accuracy deteriorates due to inter-cell interference
Solution Approach 1:
The writing process is segmented into a first write operation and a second write operation, each with specific voltage application sequences. This segmentation improves data writing accuracy by controlling inter-cell interference through staged programming, while the overall process remains managed by a single control circuit that coordinates both operations, balancing complexity and reliability.
Solution Approach 2:
The control circuit changes voltage parameters between the first and second write operations. The first write operation uses specific program voltages to establish an initial threshold distribution, and the second write operation uses different voltage parameters to finalize the threshold voltage distribution, thereby achieving accurate data writing despite the multi-step process.
3Reliability
If verification is performed after every write step to ensure accuracy, then the data writing accuracy is improved, but the operation time increases
Solution Approach 1:
Verification is segmented and performed only after the second write operation completes, rather than after every voltage application step. The first write operation forms an intermediate distribution that does not require verification, and only the final second write operation is verified. This approach maintains data writing accuracy while significantly reducing the total verification time compared to verifying after each step.
Solution Approach 2:
Instead of performing full verification after every write step (excessive action), the system performs verification only where absolutely necessary - after the final second write operation that establishes the actual data state. This partial verification approach is sufficient to ensure data accuracy while minimizing time loss.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n≧3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation.