NAND Flash Memory Cell Writing Sequence to Reduce Capacitance Coupling
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Solution Overview
Problem
Miniaturization of NAND flash memory cells leads to increased interference between adjacent cells due to capacitance coupling, causing changes in threshold values during writing operations, which results in operation errors.
Innovation Solution
The non-volatile semiconductor memory device performs a first writing operation on selected memory cells and then a second writing operation on adjacent cells, with specific voltage application methods to minimize interference and correct threshold value changes, including the use of a local self-boosting scheme and adjusted voltage levels in the second writing operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase integration density, then storage capacity per area is improved, but interference between adjacent cells increases due to capacitance coupling
Solution Approach 1:
The patent applies preliminary action by performing a first writing operation on non-selected memory cells adjacent to the selected cell before performing the second writing operation on the selected cell. This preliminary action pre-charges or pre-discharges the floating gates of adjacent cells, thereby reducing capacitance coupling interference during the subsequent writing operation on the selected cell.
Solution Approach 2:
The patent changes operational parameters by using different voltage levels for different writing operations. Specifically, it uses a first voltage level for writing to non-selected adjacent cells and a second voltage level for writing to the selected cell. This parameter change allows optimization of the writing process to minimize interference while maintaining effective data storage.
2Productivity
If writing operation is performed on a selected memory cell, then data is written to the cell, but threshold value of the cell changes due to capacitance coupling with adjacent cells
Solution Approach 1:
The patent performs preliminary writing operations on adjacent non-selected cells before writing to the selected cell. This preliminary action prepares the electrical state of surrounding cells, creating a controlled environment that prevents unwanted threshold value shifts in the selected cell during the actual writing operation.
Solution Approach 2:
The patent introduces an intermediary step by performing writing operations on non-selected adjacent cells as a mediator between the initial state and the final writing operation. This intermediary action controls the electrical environment and prevents direct harmful capacitance coupling effects from affecting the selected cell's threshold value.
3Device complexity
If conventional writing operation is used without considering cell order, then writing process is simple, but interference between adjacent cells causes operation errors
Solution Approach 1:
The patent segments the writing process into distinct phases: a first writing operation on non-selected adjacent cells and a second writing operation on the selected cell. This segmentation allows each operation to be optimized independently, ensuring reliable data storage while maintaining manageable process complexity.
Solution Approach 2:
The patent maintains continuity of useful action by performing writing operations in a continuous sequence without idle periods. The first writing operation on adjacent cells immediately precedes the second writing operation on the selected cell, ensuring that the electrical environment is continuously controlled to prevent interference throughout the entire writing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces interference between memory cells, maintaining the integrity of threshold values and preventing operation errors, even as memory cell size decreases, by sequencing writing operations and applying optimized voltages.
Implementation Method 1
the floating gate of the memory cell is capacitively coupled between the control gate (word line) provided on the floating gate and the substrate (channel) provided immediately below the floating gate
Implementation Method 2
data '0' indicating a state in which electrons are injected into the floating gate and a threshold voltage is high and data '1' indicating a state in which electrons are emitted from the floating gate
Data Source
AI summary
A non-volatile semiconductor memory device includes a plurality of cell units and a data writing unit. The cell unit includes first and second select gate transistors and a memory string including a plurality of memory cells. The data writing unit sequentially writes lower page data and upper page data corresponding to the lower page data to a selected memory cell selected in order from one close to the first select gate transistor to the second select gate transistor, and performs a first writing operation of writing the lower page data to the selected memory cell and a second writing operation of writing the upper page data to the selected memory cell after the first writing operation for n (n is an integer equal to or greater than 2) non-selected memory cells which are adjacent to a side of the selected memory cell close to the second select gate transistor.