NAND Flash XNOR Control Using Word Line Voltage Switching
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Solution Overview
Problem
Existing NAND flash memory designs are incompatible with XNOR operations due to the connection of one sense amplifier to two bit lines and separate switches for each bit line, increasing area costs.
Innovation Solution
A control method for NAND flash memory that allows XNOR operations by connecting sense amplifiers to bit lines in a one-to-one correspondence, selecting synaptic strings and memory cells for data writing with inverted data, and applying different potential voltages to word lines to read and output operation data, compatible with the normal NAND flash memory structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If one sense amplifier is connected to two bit lines with separate switches for each bit line, then XNOR operation can be completed, but the area cost increases and it becomes incompatible with normal NAND flash memory structure
Solution Approach 1:
The patent makes the sense amplifier universal by enabling it to handle both normal read operations and XNOR operations through the same hardware structure. By applying different voltage levels to word lines and utilizing the natural state of memory cells, the sense amplifier performs multiple functions without requiring dedicated hardware for XNOR operations, thus avoiding area increase while achieving operational versatility.
Solution Approach 2:
The patent changes the voltage parameters of word lines to enable XNOR operation. By applying specific voltage levels (e.g., 0V or Vpp) to different word lines during read operations, the system can perform XNOR logic operations using the existing sense amplifier and memory cell structure, transforming the function through parameter adjustment rather than structural modification.
2Adaptability or versatility
If one sense amplifier is connected to two bit lines, then XNOR operation can be completed, but it becomes incompatible with normal NAND flash memory structure
Solution Approach 1:
The patent makes the sense amplifier universal by enabling it to handle both normal read operations and XNOR operations through the same hardware structure. By applying different voltage levels to word lines and utilizing the natural state of memory cells, the sense amplifier performs multiple functions without requiring dedicated hardware for XNOR operations, thus avoiding area increase while achieving operational versatility.
Solution Approach 2:
Instead of modifying the sense amplifier connection structure to enable XNOR operations, the patent inverts the approach by keeping the sense amplifier connected to only one bit line and using word line voltage control to achieve XNOR functionality. This inversion maintains structural simplicity and compatibility while achieving the desired operational capability.
3Adaptability or versatility
If separate switches are used for each bit line, then XNOR operation can be completed, but the area cost increases
Solution Approach 1:
The patent makes the sense amplifier universal by enabling it to handle both normal read operations and XNOR operations through the same hardware structure. By applying different voltage levels to word lines and utilizing the natural state of memory cells, the sense amplifier performs multiple functions without requiring dedicated hardware for XNOR operations, thus avoiding area increase while achieving operational versatility.
Solution Approach 2:
The patent extracts the XNOR operation capability from the physical hardware structure and implements it through control signals and voltage levels. By removing the need for separate switches and dedicated XNOR circuitry, the invention achieves logical operations through software/firmware control of the existing hardware, eliminating unnecessary area consumption.
Data Source
AI summary
The present invention provides a control method for an NAND flash memory to complete an XNOR operation, including: providing an NAND flash memory, where the NAND flash memory includes at least one memory block and multiple sense amplifiers, the memory block includes multiple synaptic strings, multiple bit lines and multiple word lines, the synaptic string includes multiple memory cells connected in series, the synaptic strings are connected to the bit lines in one-to-one correspondence, the word lines are all connected to all the synaptic strings, and the sense amplifiers are connected to the bit lines in one-to-one correspondence, thereby completing the XNOR operation of the NAND flash memory by controlling a storage mode of data and a voltage of the word line.