NAND Flash Memory Zone Bit Scan for Fail Detection
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Solution Overview
Problem
In NAND flash memory, the existing bit scan method for detecting fail bits is limited by scanning an entire page at once, which restricts the increase in the number of allowable fail bits as micropatterning and multilevel cell technologies advance, leading to inefficiencies in write operations.
Innovation Solution
The proposed zone bit scan method divides a page into predetermined zones, counts fail bits in each zone, and determines if the number of fail bits is within the allowable limit, allowing for a larger number of allowable bits across the entire page by selectively scanning and skipping zones without failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire page is scanned at once using the bit scan method, then the fail bit detection is straightforward, but the number of allowable fail bits is limited and write operation time increases
Solution Approach 1:
The patent divides the memory page into multiple zones (e.g., Zone 0, Zone 1, Zone 2, etc.) and performs scan operations on each zone separately rather than scanning the entire page at once. This segmentation allows the system to process smaller portions of data sequentially, reducing the time required for each scan operation while maintaining accurate fail bit detection across the entire page.
2Quantity of substance
If the number of allowable fail bits is increased to accommodate micropatterning and multilevel cell technologies, then more data can be written, but the scan operation time increases when scanning the entire page
Solution Approach 1:
By dividing the page into zones and scanning each zone separately, the patent enables the system to handle a larger total number of allowable fail bits across the entire page without proportionally increasing scan time. The segmented approach allows parallel or sequential processing of zones, making the scan operation more scalable.
Solution Approach 2:
The patent implements a mechanism to skip scan operations on zones that have already been determined to contain no fail bits. Once a zone is scanned and confirmed to have zero fail bits, subsequent scan operations can skip that zone entirely, significantly reducing the total scan time when dealing with pages that have a large number of allowable fail bits.
3Quantity of substance
If the page length is increased to accommodate more data, then the storage capacity increases, but the scan operation time increases proportionally
Solution Approach 1:
The patent divides longer pages into multiple zones, allowing the scan operation to process the page in smaller chunks. This segmentation reduces the time required to scan each individual zone, making the overall scan operation more efficient even for pages with increased length and capacity.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array, a write control circuit, a latch circuit, an address control circuit, a scan control circuit, and an address latch circuit. The write control circuit executes write and verify for each page of the memory cell array. The latch circuit holds data of the verify result. The address control circuit divides the page into zones and sequentially selects the address of each of the zones. The scan control circuit executes scan so as to count the number of fail bits in zone selected by the address control circuit and determine whether the number of fail bits is not more than the number of allowable bits. The address latch circuit holds the address of a no fail zone, out of the plurality of zones, in which the number of fail bits is 0.