NAND Control Die Floorplan with Stacked Column Circuitry
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Solution Overview
Problem
The conventional floorplans for semiconductor memory devices face challenges in routing electrical connections, leading to increased die size and cost due to the overlap of column control circuitry and system control circuitry, which occupies substantial space.
Innovation Solution
The proposed solution involves a stacked column control circuitry arrangement where first and second column control circuitries are stacked in the x-direction, with system control circuitry positioned beside them, allowing for additional routing above the system control circuitry and reducing the size of the control die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If column control circuitry and system control circuitry are arranged in conventional floorplans, then all control functions can be implemented, but the die size increases and routing becomes complex due to overlap and crossing requirements
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Column control circuitry is divided into first and second sets that are stacked vertically in the z-direction, with bit line bridges extending upward to connect to bit lines in different planes. This vertical stacking eliminates the need for routing crossings in the planar domain, reducing routing complexity while compacting the horizontal footprint of the control die.
Solution Approach 2:
The column control circuitry is segmented into first column control circuitry associated with first bit lines and second column control circuitry associated with second bit lines. These segmented units are stacked vertically and can be independently routed to their respective bit line sets, simplifying the routing architecture by avoiding complex cross-connections that would be required in a monolithic planar layout.
2Ease of operation
If column control circuitry is distributed across multiple units, then bit line control is improved, but the overall control circuitry occupies more die area
Solution Approach 1:
Multiple column control circuitry units that would traditionally be distributed horizontally across the die are instead stacked vertically in the z-direction. This maintains the functional distribution needed for efficient bit line control while consolidating the horizontal footprint, as the stacked units occupy the same x-y plane region rather than spreading out laterally.
Data Source
AI summary
Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a second set of bit lines. The second column control circuitry is stacked in an x-direction with the first column control circuitry. The control die also has system control circuitry configured to control the first column control circuitry and the second column control circuitry. The system control circuitry resides in the floorplan beside the stacked column control circuitry to allow for additional routing of electrical connections above the system control circuitry.