Memory Interface Frequency Conversion for NAND Throughput Limits
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Solution Overview
Problem
The increasing data throughput in computing systems often exceeds the data bandwidth or communication speed of interfaces connected to non-volatile memory devices, leading to data bottlenecks and performance degradation in systems like solid-state drives (SSDs).
Innovation Solution
The implementation of an interface circuit with a deserializer and serializer that performs operating frequency conversion, allowing non-volatile memories to operate at a reduced frequency, and a training control unit that determines a delay clock value for synchronization, reducing loading between the memory controller and non-volatile memories and ensuring proper data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-volatile memory devices are connected via SATA or PCI-express interface, then the system achieves basic data transfer capability, but data throughput becomes limited by interface bandwidth causing data bottlenecks
Solution Approach 1:
The interface circuit segments the data transfer process by separating receive operations (deserialization) from transmit operations (serialization). The memory device divides incoming parallel data into multiple channels and transmits them sequentially, allowing the interface to operate at lower speeds while maintaining high overall throughput through parallel processing of multiple data streams.
Solution Approach 2:
The patent changes the operational parameters of the memory device by allowing it to operate at reduced frequencies (e.g., dividing the input clock frequency by 2 or 4) while compensating with increased data width through parallel channels. This parameter transformation enables high throughput without requiring proportionally high interface speeds.
2Productivity
If the memory device operates at reduced frequency to reduce loading on the interface, then interface bandwidth pressure decreases, but synchronization between the interface circuit and memory device becomes more challenging
Solution Approach 1:
The patent implements a training mode that performs preliminary synchronization actions before normal data transfer begins. The training control unit adjusts timing parameters and establishes phase relationships between the interface circuit and memory device clocks in advance, ensuring reliable synchronization is achieved before high-speed data transfer commences.
Solution Approach 2:
The training control unit employs feedback mechanisms to monitor the synchronization status between the interface circuit and memory device, dynamically adjusting timing parameters based on detected phase differences or skew. This closed-loop control ensures reliable data transfer even when operating at reduced frequencies with complex timing requirements.
Data Source
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AI summary
A memory system (400) includes a memory device (300) including a plurality of non-volatile memories (320_1, 320_N) and an interface circuit (310) connected to each of the plurality of non-volatile memories (320_1, 320_N), and a memory controller (200) connected to the interface circuit (310) and configured to transmit/receive data according to a first clock, wherein the interface circuit (310) is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories (320_1, 320_N) , and transmit/receive data to/from each of the plurality of non-volatile memories (320_1, 320_N) , according to the second clock.