Frequency-Band I/O Modulation for Parallel NAND Throughput
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Solution Overview
Problem
Conventional memory die architectures limit I/O throughput to the rate of a single active memory die due to shared data I/O lines, bottlenecking overall system performance as data transfer rates increase.
Innovation Solution
An I/O modulation scheme that separates I/O data into non-overlapping frequency bands, allowing multiple memory dies to operate in parallel, thereby increasing total I/O throughput proportional to the number of memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory dies are connected to shared data I/O lines, then device complexity is reduced and ease of operation is improved, but I/O throughput is limited to single-die rate causing productivity degradation
Solution Approach 1:
The patent segments the I/O interface into multiple independent lanes, where each lane can independently communicate with a separate memory die. This segmentation allows multiple dies to operate in parallel without sharing the same data path, thereby increasing total I/O throughput while maintaining manageable complexity through modular lane design
Solution Approach 2:
The patent transitions from a single-dimensional shared I/O bus to a multi-dimensional parallel lane structure. By adding the dimension of spatial parallelism across multiple lanes and dies, the system achieves higher throughput without proportionally increasing interface complexity, as each lane operates independently with its own protocol state machine
2Speed
If data transfer rates on I/O interface are increased, then speed is improved, but the ability to utilize increased rates deteriorates due to die stack limitations
Solution Approach 1:
The patent merges multiple high-speed I/O lanes with multiple memory dies in a parallel configuration, where each die can independently utilize the full data transfer rate capability. This combining of multiple high-speed paths achieves effective aggregate throughput that matches the theoretical speed potential of the interface
3Loss of time
If multiple memory dies operate on shared I/O lines, then device complexity is reduced, but loss of time occurs due to sequential access requirements
Solution Approach 1:
The patent segments the I/O controller into multiple independent channel controllers, each capable of independently managing communication with a specific memory die. This segmentation eliminates sequential access requirements by allowing parallel I/O operations across different channels, thereby reducing wait time while keeping each individual channel controller relatively simple
Data Source
AI summary
Systems and methods disclosed herein provide a modulation scheme that enables memory dies of a memory stack to occupy a shared data line in parallel, which increases data throughput within the memory stack. The systems and methods disclosed herein modulate data input/output (I/O) signals to convert the data I/O signals from a first domain to a second domain. Each data I/O signal corresponds to a memory die. The data I/O signals are separated onto channels that are non-overlapping in the second domain and are supplied simultaneously to a data line. By separating the data I/O signal onto non-overlapping channels, the plurality of memory dies can be operated in parallel at approximately the same time. In an illustrative example, the first domain is the time domain and the second domain is the frequency domain, which the channels being separate, non-overlapping frequency bands.