3D NAND Gate Electrode Division Patterns to Prevent Cell Bending
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of stacks of memory cells in semiconductor devices increases, the cells can become bent, leading to deteriorated electrical and mechanical characteristics, which affects data storage capacity and efficiency.
Innovation Solution
A semiconductor device design featuring a gate electrode structure with specific division patterns and a method of manufacturing that includes alternately stacking insulation and sacrificial layers to form a mold layer, allowing for the formation of gate electrodes with enhanced electrical characteristics and improved data storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacks of memory cells is increased to enhance data storage capacity, then the data storage capacity is improved, but the memory cells become bent according to the shapes of underlying structures, causing deterioration of electrical and mechanical characteristics
Solution Approach 1:
The gate electrode structure is divided into multiple gate electrodes spaced apart from each other in the first direction. This segmentation allows each gate electrode to be independently formed and controlled, preventing the bending issue that occurs in continuous gate structures while maintaining the necessary electrical functionality for high-capacity data storage
Solution Approach 2:
Division patterns are introduced as intermediary structures between the gate electrodes and the underlying memory cell stacks. These division patterns serve as mediators that support the gate electrodes and prevent them from bending according to the shapes of underlying structures, thereby maintaining electrical and mechanical characteristics while enabling increased stacking
2Ease of manufacture
If sacrificial layers are excessively removed to form gate electrodes, then the gate electrode structure can be formed, but process margins are reduced and manufacturing precision is compromised
Solution Approach 1:
The division patterns are formed in advance before the gate electrodes are created. This preliminary action establishes precise boundaries and support structures that guide the subsequent gate electrode formation process, ensuring that sacrificial layers are removed only to the necessary extent without excessive removal, thereby maintaining process margins and manufacturing precision
Solution Approach 2:
The invention changes the parameters of the gate electrode structure by spacing multiple gate electrodes apart from each other in the first direction rather than forming a continuous structure. This parameter change allows for controlled removal of sacrificial layers while maintaining adequate process margins and achieving the desired gate electrode functionality
Data Source
AI summary
A semiconductor device includes a gate electrode structure, a channel, first division patterns, and a second division pattern. The gate electrode structure is on a substrate, and includes gate electrodes stacked in a first direction perpendicular to the substrate. Each gate electrode extends in a second direction parallel to the substrate. The channel extends in the first direction through the gate electrode structure. The first division patterns are spaced apart from each other in the second direction, and each first division pattern extends in the second direction through the gate electrode structure. The second division pattern is between the first division patterns, and the second division pattern and the first division patterns together divide a first gate electrode in a third direction parallel to the substrate and crossing the second direction. The second division pattern has an outer contour that is a curve in a plan view.