NAND Gate Impedance Balancing for Data-Independent Delay
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Solution Overview
Problem
Conventional logic gates, such as CMOS NOR, OR, AND, and NAND gates, exhibit asymmetric pull-up/pull-down networks leading to output signal delay disparities based on input data patterns, resulting in non-uniform logic signal delays.
Innovation Solution
Designing logic gates with pull-up and pull-down networks that maintain uniform impedances independent of input data values, ensuring consistent logic signal delays across all input combinations, achieved through the use of symmetric transistor configurations and reference voltage interfaces in CMOS logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional asymmetric pull-up/pull-down networks are used in logic gates, then the circuit complexity is reduced, but the output signal delay varies depending on input data patterns
Solution Approach 1:
The patent applies asymmetry in reverse - it deliberately introduces symmetric elements (dummy transistors) into an inherently asymmetric circuit structure to balance the pull-up and pull-down network impedances. This creates a balanced configuration where the total impedance of pull-up network equals the total impedance of pull-down network, ensuring uniform output delay regardless of input data patterns.
Solution Approach 2:
The patent changes the impedance parameter of the pull-up and pull-down networks by adding dummy transistors with specific resistance values. The dummy transistors are sized to provide precise resistance values that balance the total impedance of both networks, transforming the asymmetric impedance characteristics into symmetric ones to achieve data-independent delay.
2Reliability
If symmetric transistor configurations are used to achieve uniform impedance, then the output signal delay becomes independent of input data, but the device complexity increases
Solution Approach 1:
The patent introduces dummy transistors as intermediary elements that mediate between the asymmetric input signals and the output. These dummy transistors act as compensating elements that balance the impedance differences caused by varying input data patterns, serving as a buffer that equalizes the electrical characteristics of both pull-up and pull-down networks.
Solution Approach 2:
The patent segments the pull-up and pull-down networks into distinct functional blocks with separately controllable impedance characteristics. By dividing the circuit into these segments and independently sizing the dummy transistors in each segment, the design achieves balanced total impedance while maintaining modularity and manageable complexity.
Data Source
AI summary
Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.