3D NAND Gate Stack Layout for Reliable Vertical Contacts
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Solution Overview
Problem
There is a need for semiconductor devices with improved data storage capacity and reliability.
Innovation Solution
A semiconductor device design featuring a stacked structure with gate electrodes, interlayer insulating layers, and contact plugs that extend in a vertical direction, including a gate contact region and contact insulating layers to enhance electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs directly penetrate gate electrodes and interlayer insulating layers without additional contact insulating layers, then manufacturing process is simpler, but electrical connectivity and reliability are compromised
Solution Approach 1:
The patent introduces contact insulating layers as intermediary elements between the contact plugs and the gate electrodes/interlayer insulating layers. These contact insulating layers serve as mediator structures that improve electrical connectivity and reliability while managing the complexity through systematic layer integration into the existing stacked architecture.
2Quantity of substance
If gate electrodes extend by different lengths in horizontal direction, then data storage capacity and integration density increase, but manufacturing precision and alignment difficulty increase
Solution Approach 1:
The patent segments the gate electrode structure into multiple regions with different horizontal extension lengths, allowing each segment to be optimized for specific functions. This segmentation enables increased integration density and data storage capacity while maintaining manufacturability through region-specific design approaches.
Solution Approach 2:
The patent applies local quality by giving different regions of the gate electrode structure different properties - specifically, different horizontal extension lengths in different regions. This allows optimization of electrical connectivity and data storage capacity in specific areas without compromising the overall structural integrity or manufacturing feasibility.
3Productivity
If vertical stacked structure is implemented with multiple layers, then integration density increases, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent transitions from planar two-dimensional device architecture to three-dimensional vertical stacked structure. By stacking gate electrodes, interlayer insulating layers, and contact plugs vertically, the patent achieves higher integration density by utilizing the vertical dimension, thereby increasing productivity and data storage capacity.
Solution Approach 2:
The patent implements a nested doll structure where multiple functional layers are stacked vertically - contact insulating layers are nested within the broader stack of gate electrodes and interlayer insulating layers. This nested arrangement maximizes space utilization and integration density while organizing complex manufacturing processes into hierarchical layers.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnections on the circuit devices, and a second semiconductor structure on the first semiconductor structure and having first and second regions. The second semiconductor structure including a plate layer, gate electrodes stacked and spaced apart from each other on an upper surface of the plate layer in a vertical direction, extending by different lengths on the second region in a first direction intersecting the vertical direction, and including a gate contact region, interlayer insulating layers stacked alternately with the gate electrodes, a channel structure penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction, contact plugs penetrating the gate electrodes in the second region, extending in the vertical direction, and electrically connecting the gate electrodes to a portion of the circuit interconnections, respectively.