3D NAND Memory Gate Stack Insulator Positioning

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Solution Overview

Problem

Conventional two-dimensional NAND flash memory devices face challenges in miniaturization due to issues like the short channel effect, interdevice interference, and interdevice variations, which affect storage density and lead to read errors caused by tunnel insulating layer damage during repeated write/erase operations.

Innovation Solution

A nonvolatile semiconductor memory device with a three-dimensional structure featuring a gate stacked layer structure where a block insulating layer is positioned closer to the active area layers and a tunnel insulating layer with a smaller equivalent oxide thickness is positioned closer to the control gate electrode, reducing the influence of trapped charge on threshold voltage and channel current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the memory device uses a conventional two-dimensional NAND structure, then manufacturing and layout are simpler, but storage density cannot be sufficiently increased and miniaturization is limited due to short channel effect and interdevice interference

Engineering Contradiction:

Improvestorage densityVSAvoidstructure complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from a conventional two-dimensional planar structure to a three-dimensional vertical gate structure. The gate electrode extends vertically through the thickness of the semiconductor layer, creating a vertical channel that enables higher storage density by utilizing the third dimension (depth) rather than only the planar surface area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If the tunnel insulating layer is made thinner to improve charge transfer efficiency, then write/erase operations are faster, but the layer becomes more susceptible to damage from repeated operations causing read errors

Engineering Contradiction:

Improvewrite/erase operation speedVSAvoidread operation reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies different insulating materials with different properties to different regions of the gate structure. The tunnel insulating layer uses a first material (e.g., silicon oxide) optimized for charge transfer, while the block insulating layer uses a second material (e.g., silicon nitride) with higher breakdown strength to prevent damage propagation. This local differentiation allows the tunnel layer to be thin for fast operation while the block layer provides robust protection.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The gate insulating structure employs a composite of two different insulating materials: a tunnel insulating layer and a block insulating layer. This composite structure combines the high charge transfer efficiency of the tunnel layer with the high breakdown strength of the block layer, achieving both fast write/erase operations and reliable read operations even after repeated cycles.

Inventive Principle:

Principle #40Composite materials

3Reliability

If charge storage layers are made electrically floating (VG-FG type), then charge trapping is improved, but charge trapped in damaged tunnel insulating layer varies threshold voltage causing read errors

Engineering Contradiction:

Improvecharge storage reliabilityVSAvoidthreshold voltage variation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The block insulating layer acts as an intermediary barrier between the tunnel insulating layer and the floating gate electrode. When the tunnel layer becomes damaged and traps charge, the block insulating layer prevents this trapped charge from directly affecting the threshold voltage of the memory cell, thereby maintaining read operation reliability even after repeated write/erase cycles.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability of the memory device by minimizing the impact of trapped charge on threshold voltage and channel current, preventing read errors and improving storage density.

Implementation Method 1

writing and erasing of data are performed by a charge transfer between the semiconductor layer as a channel and the floating gate electrode

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

the tunnel insulating layer is damaged (defective), and charge is trapped in the damaged part

Methodology Applied

Scientific EffectCharge trapping:

Data Source

PatentUS9373631B2Nonvolatile semiconductor memory device

Publication Date: 2016.06.21 KIOXIA CORP

AI summary

According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to nth semiconductor layers (n is a natural number greater than or equal to 2) stacked in a first direction, and extending in a second direction, and first to nth memory cells provided on surfaces of the first to nth semiconductor layers facing a third direction. The ith memory cell (1≦i≦n) comprises a second stacked layer structure in which a first insulating layer, a charge storage layer, a second insulating layer, and a control gate electrode are stacked. The second insulating layer has an equivalent oxide thickness smaller than that of the first insulating layer.