3D NAND Gate Stack and Contact Plug Layout for Reliable Scaling
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining reliability, particularly in the design and structure of memory cells and interconnection layers.
Innovation Solution
The semiconductor device incorporates a unique structure with stacked gate electrodes, horizontal insulating layers, channel structures, and dummy vertical structures, along with contact plugs and cell region insulating layers, to enhance data storage capacity and reliability by optimizing the arrangement and materials of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements three-dimensional memory cell arrangement by stacking gate electrodes (lower select gate electrode, memory gate electrode, upper select gate electrode) vertically over a plate layer, transitioning from two-dimensional to three-dimensional spatial utilization to increase storage capacity without proportionally increasing device footprint
Solution Approach 2:
The memory device is segmented into distinct functional regions including first and second regions with different channel structure configurations, allowing independent optimization of each region while managing overall device complexity through modular design
2Reliability
If contact plugs penetrate through gate electrodes to connect circuit interconnection lines, then electrical connection is improved, but manufacturing precision requirements increase
Solution Approach 1:
Dummy vertical structures are formed in advance around contact plugs before final connection establishment, serving as preliminary protective and guiding structures that facilitate precise contact plug formation and reduce manufacturing variability
Solution Approach 2:
Dummy vertical structures act as intermediary elements between the contact plugs and surrounding structures, providing a buffer zone that simplifies the alignment and connection process while ensuring reliable electrical contact
3Stability of the object's composition
If dummy vertical structures are added around contact plugs, then structural integrity is improved, but device complexity increases
Solution Approach 1:
Dummy vertical structures are positioned around contact plugs to provide beforehand cushioning and protection, preventing structural damage during manufacturing and operation while maintaining overall device stability
Data Source
AI summary
The present disclosure relates to semiconductor devices, in which a semiconductor device includes: a plate layer, gate electrodes stacked and spaced apart from each other on the plate layer in a first direction, the gate electrodes including first gate electrodes and second gate electrodes on the first gate electrodes; a horizontal insulating layer between the first gate electrodes and the second gate electrode; first channel structures extending through the first gate electrodes in the first direction; second channel structures extending through the second gate electrodes in the first direction and electrically connected to the first channel structures, respectively; contact plugs extending through the horizontal insulating layer in the first direction and connected to the gate electrodes, respectively; dummy vertical structures extending through the horizontal insulating layer in the first direction and around the contact plugs, and a cell region insulating layer covering upper surfaces of the dummy vertical structures.