NAND Flash Memory Erase Using Dynamic GIDL Voltage Control

Solution Overview

Problem

Existing erase operations in NAND flash memory devices face inefficiencies due to high voltage requirements and potential degradation of gate-induced drain leakage (GIDL) generators, leading to prolonged erase times and potential damage.

Innovation Solution

A method is introduced to generate GIDL current using controlled voltage differentials across gate-induced drain leakage (GIDL) generators, optimizing the voltage levels to minimize high longitudinal electric fields and facilitate efficient erase operations while reducing stress on the generators.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high erase voltages (20V or more) are applied to complete erase operations, then erase completeness is improved, but generator degradation and erase time increase

Engineering Contradiction:

Improveerase completenessVSAvoiderase time

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent applies dynamic voltage adjustment by ramping up the erase voltage from a lower initial level to a higher final level during the erase operation. This dynamic approach allows the system to achieve complete erase (improving reliability) while minimizing the time spent at high voltage levels (reducing duration), thereby resolving the contradiction between erase completeness and erase time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary actions by applying a lower voltage initially to prepare the memory cells for erasure before applying the full high voltage. This preliminary low-voltage phase reduces the stress on GIDL generators and allows the subsequent high-voltage phase to be more effective and shorter in duration, thus improving erase completeness while controlling erase time.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If high erase voltages (20V or more) are applied to complete erase operations, then erase completeness is improved, but generator degradation increases

Engineering Contradiction:

Improveerase completenessVSAvoidgenerator degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent performs preliminary actions by applying a lower voltage initially to prepare the memory cells for erasure before applying the full high voltage. This preliminary low-voltage phase reduces the stress on GIDL generators and allows the subsequent high-voltage phase to be more effective and shorter in duration, thus improving erase completeness while controlling erase time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies dynamic voltage adjustment by ramping up the erase voltage from a lower initial level to a higher final level during the erase operation. This dynamic approach allows the system to achieve complete erase (improving reliability) while minimizing the time spent at high voltage levels (reducing duration), thereby resolving the contradiction between erase completeness and erase time.

Inventive Principle:

Principle #15Dynamics

3Reliability

If voltage levels are optimized to reduce GIDL generator stress, then generator reliability is improved, but erase efficiency may decrease

Engineering Contradiction:

Improvegenerator reliabilityVSAvoiderase efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamic voltage adjustment by ramping up the erase voltage from a lower initial level to a higher final level during the erase operation. This dynamic approach allows the system to achieve complete erase (improving reliability) while minimizing the time spent at high voltage levels (reducing duration), thereby resolving the contradiction between erase completeness and erase time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter dynamically during the erase operation, transitioning from a lower initial voltage to a higher final voltage. This parameter change strategy allows the system to balance generator reliability (by limiting exposure to high voltage) with erase efficiency (by achieving sufficient erase at the higher voltage level).

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances erase efficiency by maintaining consistent GIDL current levels throughout the erase process, potentially shortening erase times and reducing generator degradation, thus improving the reliability and performance of NAND flash memory devices.

Implementation Method 1

A method is introduced to generate GIDL current using controlled voltage differentials across gate-induced drain leakage (GIDL) generators

Methodology Applied

Scientific EffectGate-induced drain leakage (GIDL): Avalanche Breakdown

Data Source

PatentEP4022617B1Erasing memory

Publication Date: 2025.10.15 MICRON TECHNOLOGY INC

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AI summary

Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.