3D NAND GSL Region Layout for Interference-Resistant Cell Strings
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Solution Overview
Problem
As memory devices integrate vertically, interference between word lines, string select lines, and ground select lines increases, deteriorating data reliability, and physical separation of ground select lines through dummy holes degrades integration and affects memory cell characteristics.
Innovation Solution
A memory device with a ground select line (GSL) region that electrically separates cell strings, using ground select transistors with programmed threshold voltages and dummy lines to improve channel potential boundary characteristics, reducing interference and enhancing data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ground select lines are physically separated using dummy holes, then interference between cell strings is reduced, but integration is deteriorated and memory cell characteristics are degraded
Solution Approach 1:
The ground select lines are segmented into multiple regions along the vertical channel, with dummy lines inserted between adjacent ground select lines to create electrical isolation. This segmentation approach divides the continuous ground select line into discrete segments that can be independently controlled, reducing interference while maintaining integration.
Solution Approach 2:
Dummy lines are introduced as intermediary elements between adjacent ground select lines. These dummy lines act as mediators that electrically isolate the ground select lines from each other, preventing direct interference while maintaining the physical continuity of the memory structure without requiring dummy holes.
2Reliability
If ground select lines are electrically separated, then data reliability is improved, but memory cell characteristics are degraded due to hot carrier injection
Solution Approach 1:
Different threshold voltage distributions are applied to different dummy lines based on their local positions and functions. Dummy lines adjacent to ground select lines use one threshold voltage distribution to minimize hot carrier injection, while dummy lines in other positions use different distributions optimized for their specific locations, achieving localized optimization of electrical separation.
3Productivity
If more word lines are stacked vertically, then memory device integration is improved, but interference between word lines increases
Solution Approach 1:
The isolation mechanism is extended from two-dimensional planar separation to three-dimensional vertical separation by inserting dummy lines at different height levels within the vertical channel structure. This multi-level dimensional approach allows electrical isolation to be implemented in the vertical dimension, accommodating higher integration of word lines while maintaining data reliability.
Data Source
AI summary
A memory device includes an array of memory cells having a plurality of cell strings therein electrically coupled to a ground select line (GSL) region. This region includes: a plurality of rows of ground select transistors having programmable threshold voltages, a first row of dummy memory cells extending immediately adjacent a first one of the plurality of rows of ground select transistors and programmed to have threshold voltages within a first threshold voltage distribution, and a second row of dummy memory cells extending immediately adjacent a second one of the plurality of rows of ground select transistors. The second row of dummy memory cells are programmed to have threshold voltages within a second threshold voltage distribution, which has a center threshold voltage that is spaced apart from a center threshold voltage within the first threshold voltage distribution, on a threshold voltage scale.