3D NAND GSL Threshold Layout for Line Interference Control
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Solution Overview
Problem
The increase in integration density of memory devices leads to interference among word lines, string select lines, and ground select lines, degrading the reliability of data storage.
Innovation Solution
A memory device design with a memory cell array comprising cell blocks, where ground select transistors in different cell blocks are programmed to distinct threshold voltages, and a control circuitry controls operations to maintain reliability, including a GSL region with vertically stacked transistors and dummy lines to enhance electrical separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration density of memory devices is increased, then the storage capacity is improved, but the interference among word lines, string select lines, and ground select lines increases, degrading data reliability
Solution Approach 1:
The patent applies local quality by differentiating the threshold voltages of ground select transistors based on their operational requirements. Transistors connected to GSLs are programmed to a first threshold voltage, while those not connected to GSLs are programmed to a second threshold voltage. This localized differentiation allows optimized performance for specific regions without compromising overall data reliability, resolving the contradiction between high integration density and data reliability.
2Volume of moving object
If the number of word lines stacked in vertical direction is increased, then the integration density is improved, but the interference among lines increases
Solution Approach 1:
The patent introduces dummy lines as intermediary elements between word lines in the vertical stack. These dummy lines act as electrical isolators that reduce direct coupling and interference between adjacent word lines, enabling higher vertical stacking capacity while mitigating the harmful interference effects that would otherwise degrade data reliability.
Data Source
AI summary
A memory device comprises: a memory cell array including a plurality of cell blocks including a first cell block storing information other than user data and a second cell block storing the user data, wherein each of the plurality of cell blocks includes a plurality of cell strings and control circuitry configured to control a write operation and a read operation of the memory cell array. A first ground select line (GSL) region included in the first cell block includes a plurality of GSLs stacked in a vertical direction. One or more ground select transistors of a plurality of ground select transistors connected to each of the GSLs are programmed to a first threshold voltage and the other ground select transistors of the plurality of ground select transistors not connected to the GSLs are programmed to a second threshold voltage that is higher than the first threshold voltage. A first line included in the first GSL region in the first cell block is arranged at a same height as a word line connected to memory cells storing the user data in the second cell block.