Managed NAND Host Accelerated Operations Verification
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Solution Overview
Problem
Current host-aware performance booster (HPB) techniques for managed NAND devices face issues with data validation, unauthorized modifications, and proprietary operation protection, particularly in wear leveling, due to the lack of control over host memory and potential for malicious or defective software to corrupt data.
Innovation Solution
Implementing a verification mechanism using logical and physical address pairs, where the controller hashes the addresses and stores the result, allowing the host to provide the hashed addresses for verification, ensuring data integrity and protecting against replay attacks by delaying read requests in case of incorrect hashes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If host-aware performance booster (HPB) techniques are implemented without verification mechanisms, then read latency is reduced through host-provided physical addresses, but data integrity is compromised due to potential malicious or defective software corrupting data
Solution Approach 1:
The controller performs preliminary hashing of logical addresses and stores hash values in buffer memory before host read requests arrive. When a read request comes with a host-provided physical address, the controller immediately verifies by hashing the logical address and comparing with stored hash, enabling fast verification without delaying the read operation.
Solution Approach 2:
Hash values serve as an intermediary verification mechanism between the host-provided physical address and the actual data read operation. The hash comparison acts as a mediator that validates data integrity without requiring full controller intervention, enabling the host to provide accurate physical addresses while maintaining security.
2Reliability
If the controller verifies all host-provided physical addresses through traditional methods, then data integrity is ensured, but performance benefits of HPB are lost due to increased verification overhead
Solution Approach 1:
Hash values are pre-computed and stored in buffer memory during write operations or idle periods, so that during read operations the verification only requires a simple hash comparison rather than full validation. This preliminary preparation enables fast verification that maintains data integrity while preserving HPB performance benefits.
Solution Approach 2:
The verification process changes from traditional comprehensive validation to a simplified hash comparison operation. By transforming the verification parameter from full address validation to hash value comparison, the computational overhead is dramatically reduced while maintaining security, enabling fast verification that preserves HPB read performance.
3Device complexity
If the controller implements no protection against replay attacks, then device complexity is reduced, but security is compromised allowing unauthorized modifications
Solution Approach 1:
The controller pre-stores hash values in buffer memory before replay attacks can occur. When a read request arrives, the pre-stored hash is immediately compared with the hash of the provided logical address, enabling detection of replayed or tampered requests without adding complex real-time verification logic.
Solution Approach 2:
The hash value acts as a copy or fingerprint of the logical address that can be quickly compared without dealing with the full complexity of the original address validation. This copying approach simplifies the verification mechanism while maintaining security against replay attacks.
Data Source
AI summary
Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.