3D NAND Inductor Staircase Structure for High Density
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Solution Overview
Problem
Conventional on-chip inductors are difficult to realize due to the large form factors required to achieve high inductance values and quality factors (Q factor) for commercial use, and they are costly to manufacture due to the need for multiple metal levels.
Innovation Solution
The formation of an on-chip inductor using similar structures to those used in NAND memory, such as a solenoid inductor, which utilizes the staircase and pillar-like structures of NAND flash memory to achieve high inductance density and quality factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional on-chip inductors are used, then inductance values and quality factors can be achieved, but large form factors are required
Solution Approach 1:
The patent transitions from planar 2D inductor structures to three-dimensional vertical structures by stacking multiple conductive layers and dielectric layers. The inductor utilizes vertical stacking of conductive paths through multiple metal levels, creating a 3D configuration that achieves higher inductance density per unit area, thereby reducing the overall form factor while maintaining required quality factors.
Solution Approach 2:
The inductor structure embeds multiple conductive layers and dielectric layers within each other in a vertical stack configuration. Each conductive layer is nested within dielectric material, and multiple such stacks are arranged vertically to create a compact nested structure that maximizes inductance within a small footprint area.
2Reliability
If conventional on-chip inductors are used, then inductance values can be achieved, but manufacturing costs increase due to multiple metal levels
Solution Approach 1:
The inductor structure utilizes the same stacked layer architecture that is already employed in existing semiconductor manufacturing processes for creating multi-layer devices. By leveraging existing manufacturing capabilities for creating vertical stacks of conductive and dielectric layers, the inductor can be produced using standard process steps, thereby reducing additional manufacturing costs despite the complex 3D structure.
3Stress or pressure
If charge pumps are used in NAND arrays, then high voltage can be generated, but efficiency is lower compared to boost converters
Solution Approach 1:
The patent replaces the charge pump mechanism with an inductor-based voltage conversion structure. Instead of using capacitive charge transfer through switching networks, the invention employs electromagnetic induction principles through the stacked inductor structure to achieve voltage transformation, which reduces energy loss and improves conversion efficiency while still generating the required high voltages for NAND array operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of on-chip inductors with high inductance density and quality factor, overcoming the challenges of large form factors and high manufacturing costs, while also being scalable with advancements in NAND technology.
Implementation Method 1
an inductor comprising: a staircase structure having a plurality of tiers, each tier comprising a conductive layer, the plurality of tiers forming respective steps on a first side of the staircase structure
Data Source
AI summary
An inductor is formed on an integrated circuit (IC) using one or more structures formed during or in coordination with 3D NAND structure fabrication with one or more modifications. The inductor has a staircase structure, the staircase structure having a plurality of tiers that form steps on one side of the staircase structure. Each tier comprises a conductive layer. The plurality of tiers includes at least a first tier and a second tier. The inductor has a first contact electrically coupling the first tier and the second tier. A first portion of a die is occupied by a memory sub-component comprising at least one three-dimensional (3D) NAND memory component and a second portion of the die is occupied by the inductor.