NAND Flash Inter-Cell Interference Mitigation via Adjacent Cell Voltage
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Solution Overview
Problem
NAND cell type flash memory experiences increased error rates due to inter-cell interference as memory cells become finer, leading to unreliable data read operations, as conventional likelihood calculation methods do not account for the influence of adjacent memory cells' threshold voltage levels.
Innovation Solution
A memory system and control method that calculates highly accurate likelihood values by considering the threshold voltage levels of adjacent memory cells, using logarithm likelihood ratios and look-up tables to improve error correction capabilities through soft determination decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are made finer to increase storage capacity, then storage density is improved, but inter-cell interference increases leading to higher error rates
Solution Approach 1:
The patent applies local quality by making the likelihood calculation process adaptive to local conditions - specifically, by considering the threshold voltage levels of adjacent memory cells when calculating likelihood values. This localized adjustment allows the decoding process to account for inter-cell interference specific to each cell's neighborhood, thereby maintaining reliability even as cells are made finer and interference increases.
2Device complexity
If conventional likelihood calculation methods are used without considering adjacent cells, then decoding complexity is reduced, but decoding accuracy deteriorates due to unaccounted inter-cell interference
Solution Approach 1:
The patent introduces an intermediary element in the likelihood calculation process - the threshold voltage level information of adjacent memory cells. This intermediary information acts as a mediator that bridges the gap between the simple conventional calculation and the need for interference compensation. By incorporating this additional information, the system achieves higher decoding accuracy without requiring a complete redesign of the decoding architecture.
Data Source
AI summary
A memory system and method is provided. The memory system includes a non-volatile memory, a memory interface, and a code processor. The code processor generates a likelihood value for a first read bit, which is read from a first memory cell, from among read bits contained in a codeword read by the memory interface from the non-volatile memory. For example, the likelihood value can be based on the value of the first read bit and on the value of a second read bit read from a second memory cell adjacent to the first memory cell so as to decode the codeword using the generated likelihood value.